IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 16 of 16  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IN, NS
(Joint)
2019-03-05
15:40
Okinawa Okinawa Convention Center Design and evaluation of serializing method for IoT systems
Yui Saito, Keiichiro Kashiwagi, Hisaharu Ishii, Tomohiro Inoue (NTT) IN2018-148
IoT systems receive large amount of data from many sensors and devices. IoT systems require a high-throughput and resour... [more] IN2018-148
pp.385-390
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
09:30
Kanagawa Hiyoshi Campus, Keio University Implementation and Evaluation of the Low-level Communication Mechanism on FLOPS-2D
Katsuki Kyan, Makoto Arakaki, Yusuke Hirai, Hiroki Nakasone (Univ. of the Ryukyus), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.), Yasunori Osana (Univ. of the Ryukyus) VLD2014-134 CPSY2014-143 RECONF2014-67
FLOPS-2D is a multiple-FPGA computer system that consists of several FLOPS boards. Each FLOPS board has one FPGA, memory... [more] VLD2014-134 CPSY2014-143 RECONF2014-67
pp.139-143
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-27
16:00
Oita B-ConPlaza Design and Evaluation of High-speed Serial Communication Mechanism for FPGA-based ASIC Emulator
Takashi Okamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-42
The circuit scale of Application Specific Integrated Circuit(ASIC)has been increasing. Therefore the shortening of funct... [more] RECONF2014-42
pp.45-50
SWIM 2014-05-23
16:05
Tokyo Kikai-Shinko-Kaikan Bldg. A Concurrency Control Method between Batch Update and Online Entries -- An Implementation and Evaluations --
Tsukasa Kudo (Shizuoka Inst. of Science and Tech.), Yui Takeda (MDIS), Masahiko Ishino (Bunkyo Univ.), Kenji Saotome (Hosei Univ.), Nobuhiro Kataoka (Interprise Lab.) SWIM2014-6
Databases of business systems are often updated by the long batch update. To execute this as a single transaction concur... [more] SWIM2014-6
pp.31-36
DC, CPSY
(Joint)
2013-08-02
16:15
Fukuoka Kitakyushu-Kokusai-Kaigijyo A High Throughput Network Framework for Distributed CEP
Kenji Kobayashi, Toshiaki Saeki, Emeric Viel, Nobutaka Imamura, Masazumi Matsubara, Haruyasu Ueda, Yoshinori Sakamoto (Fujitsu Lab.) CPSY2013-26
Distributed CEP is big data processing platform that can process many events in real-time. In a distributed CEP system, ... [more] CPSY2013-26
pp.97-102
RECONF 2013-05-21
10:10
Kochi Kochi Prefectural Culture Hall Design and Evaluation of FPGA-based ASIC Emulator using High-speed Serial Communication
Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-10
Recently, development period of ASIC is longer becouse of the increase in circuit scale.
Verification process accounts ... [more]
RECONF2013-10
pp.49-54
HIP, HCS 2011-05-23
16:40
Okinawa Okinawa Industry Support Center Effect of complexity in kanji letters for attention blink
Hinako Yago, Minoru Nakayama (Tokyo Tech) HCS2011-11 HIP2011-11
The influence the complexity in Kanji letters on the attention blink is examined. Kanji letters in three levels of the c... [more] HCS2011-11 HIP2011-11
pp.85-89
EMCJ 2011-04-22
15:25
Hyogo University of Hyogo A Method for Predicting Characteristic of Crosstalk between Twisted Pair Cables at High Frequency
Koji Shibuya, Seiichi Saito, Yusuke Suzuki, Keitaro Yamagishi, Hiroyuki Joba (Mitsubishi Electric Corp.) EMCJ2011-6
In this paper, we paid attention to two pairs of the combinations of the twist pitches of the twisted-pair cable in the ... [more] EMCJ2011-6
pp.31-36
ICD 2011-04-19
13:10
Hyogo Kobe University Takigawa Memorial Hall [Invited Talk] A 12Gb/s Non-Contact Interface with Coupled Transmission Lines
Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.) ICD2011-14
This paper presents the novel approach for high speed non-contact memory card interfaces. The proposed scheme using coup... [more] ICD2011-14
pp.77-80
CS, SIP, CAS 2011-03-03
10:00
Okinawa Ohhamanobumoto memorial hall (Ishigaki)( Proposal of the High-Throughput and Low-Latency DMA
Tatsunori Tsujimura (Mitsubishi Electric) CAS2010-105 SIP2010-121 CS2010-75
It is necessary for Industrial Controller to transfer data by DMA (Direct Memory Access) between the memory with high ac... [more] CAS2010-105 SIP2010-121 CS2010-75
pp.19-24
RECONF 2009-09-18
09:00
Tochigi Utsunomiya Univ. A Proposal for a Method to Generate Optimized Dataflow for Reconfigurable Processor DS-HIE Based on Bit Serial Operation
Yasuhiro Nishinaga, Ken'ichi Umeda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2009-28
Our laboratory has developed a reconfigurable processor DS-HIE based on bit-serial operation. The DS-HIE processor achie... [more] RECONF2009-28
pp.55-60
RECONF 2009-09-18
09:25
Tochigi Utsunomiya Univ. Consideration of Data Transfer Unit in Reconfigurable Processor DS-HIE
Ken'ichi Umeda, Yasuhiro Nishinaga, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ) RECONF2009-29
We have developed reconfigurable processor DS-HIE based on bit-serial operation. The merit of bit-serial operation is th... [more] RECONF2009-29
pp.61-66
RECONF 2007-09-20
13:00
Shiga Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) Proposal and application of Memory with Digit-Width Converter
Yuhki Yamabe, Kazuya Tanigawa, Tetsuo Hironaka (HCU) RECONF2007-15
We research to enhance the performance of the dynamic reconfigurable processor by reducing the needs of dynamic reconfig... [more] RECONF2007-15
pp.1-6
RECONF 2007-09-20
14:00
Shiga Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) Consideration about Routing Resources for DS-HIE Architecture
Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (HCU) RECONF2007-17
We have developed DS-HIE architecture which is a dynamic reconfigurable architecture
for data streaming applications. I... [more]
RECONF2007-17
pp.13-18
DE 2007-07-02
14:55
Miyagi Akiu hot springs (Sendai) An Approach for XML Similarity Join using Tree Serialization
Lianzi Wen, Toshiyuki Amagasa, Hiroyuki Kitagawa (University of Tsukuba) DE2007-37
In this paper we propose a scheme for similarity join over XML data
based on XML data serialization and subsequent si... [more]
DE2007-37
pp.91-96
CPSY, VLD, IPSJ-SLDM 2005-01-25
10:00
Kanagawa   Reconfigurable 1-bit processor array with reduced wiring area
Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe (NAIST)
Semiconductor makers have a problem of how to reduce the production cost. Because of the increasing gates to implement a... [more] VLD2004-98 CPSY2004-64
pp.7-12
 Results 1 - 16 of 16  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan