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All Technical Committee Conferences (Searched in: Recent 10 Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, DC, RECONF, IPSJ-ARC [detail] | 2024-08-08 16:45 |
Tokushima | Awagin Hall (Tokushima, Online) (Primary: On-site, Secondary: Online) |
X-Filling and Test Scheduling Methods for Concurrent Testing Using Optimistically/Pessimistically Structural Symbolic Simulation Haruta Tokuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.)  CPSY2024-25 DC2024-25 RECONF2024-25 |
In recent years, with the increasing test cost of VLSIs, it has become important to reduce the number of test patterns. ... [more] | CPSY2024-25 DC2024-25 RECONF2024-25 pp.46-51 |
| SR | 2023-11-09 14:30 |
Miyagi | (Miyagi, Online) (Primary: On-site, Secondary: Online) |
[Technology Exhibit]
Demonstration and Experimental Results of Power Control for O-RAN Base Stations Utilizing Pedestrian Flow Analytics and Non-Terrestrial Networks Takaya Miyazawa, Kentaro Ishizu, Hitoshi Asaeda, Hiroyuki Tsuji, Hiroaki Harai (NICT) SR2023-50 |
To reduce the power consumption of terrestrial radio access networks (RANs) being compliant with Open RAN (O-RAN), we ha... [more] | SR2023-50 pp.16-21 |
| DC | 2021-02-05 14:00 |
Online | Online (Online) | Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2020-74 |
In recent years, since the test cost for large-scale integrated circuits has increased, design-for-testability methods f... [more] | DC2020-74 pp.30-35 |
| DC | 2018-02-20 09:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Tokyo) | A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation Yuki Takeuchi, Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2017-78 |
It is required to reduce the number of test patterns to reduce test cost for VLSIs. Especially, design-for-testability m... [more] | DC2017-78 pp.7-12 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 15:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea (Kumamoto) | A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) VLD2017-37 DC2017-43 |
Recently, it is very important to reduce the number of test patterns by using design-for-testability (DFT) with the incr... [more] | VLD2017-37 DC2017-43 pp.61-66 |
| CQ | 2015-07-07 13:00 |
Nara | Nara Institute of Science and Technology (Nara) | Effect of Voluntary Control against Congestion during Disaster Daisuke Satoh (NTT), Yuji Takano (Doshisha Univ.), Ryunosuke Sudo (Kyushu Univ.), Takemi Mochida (NTT) CQ2015-36 |
When a disaster strikes, many people make calls to their family and friends. As a result, a telephone network becomes co... [more] | CQ2015-36 pp.87-92 |
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