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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IA | 2023-09-21 15:05 |
Hokkaido | Hokkaido Univeristy (Primary: On-site, Secondary: Online) |
Development and Evaluation of Life Logging System Utilizing Sensor Mesh Network with Power Generation Mechanism Haoting Zhang, Hiroshi Yamamoto (Ritsumeikan Univ.)  IA2023-14 |
In order to prevent the lifestyle diseases, it is clarified that the recording of lifelog data related with the location... [more] | IA2023-14 pp.19-24 |
| RCS, SR, NS, SeMI, RCC (Joint) |
2021-07-15 09:25 |
Online | Online | Development and Evaluation of a Smart Tap Sensor Network for Observing Household Behavior Ryuichi Inoue, Hiroshi Yamamoto (Ritsumeikan Univ.) NS2021-41 |
In recent years, the devices targeting the smart home have rapidly been spreading and have been expected to be applied t... [more] | NS2021-41 pp.45-50 |
| CQ, CBE (Joint) |
2021-01-21 16:00 |
Online | Online | [Poster Presentation]
In-home Behavior Observation System Using Thread Mesh Network Ryuichi Inoue, Hiroshi Yamamoto (Ritsumeikan Univ.) CQ2020-76 |
To realize a smart home that can effectively watch over residents and control energy consumption, the technology for rec... [more] | CQ2020-76 pp.66-67 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2015-08-05 14:30 |
Oita | B-Con Plaza (Beppu) | Efficient Thread Control Method for Parallel Loop Processing by Dynamic Binary Translation Hiroyuki Obuchi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2015-29 |
In order to effectively utilize the performance of multicore processors spreading commonly at present, it is an importan... [more] | CPSY2015-29 pp.155-160 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-06 14:50 |
Kagoshima | A Resource Utilization Aware Method to Improve Throughput on RMT Processor Taro Murata, Kensuke Kaneda, Masayoshi Takasu, Keigo Mizotani, Yusuke Hatori, Nobuyuki Yamasaki (Keio Univ.) CPSY2014-166 DC2014-92 |
SMT (Simultaneous MultiThreading) architecture is suitable for embedded processors which have area constraints, it is b... [more] |
CPSY2014-166 DC2014-92 pp.25-30 |
|
| ICD, CPSY | 2014-12-01 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Poster Presentation]
A Study on a Comprehensive Architecture Exploration Environment for Emerging Applications Shohei Takeuchi, Shinya Takamaeda Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST) ICD2014-77 CPSY2014-89 |
Emerging applications, such as graph processing and machine learning, contain several irregular memory access patterns a... [more] | ICD2014-77 CPSY2014-89 pp.25-27 |
| DC, CPSY (Joint) |
2013-08-02 17:30 |
Fukuoka | Kitakyushu-Kokusai-Kaigijyo | Code Optimization for Path Based Speculative Multi-threading Yuki Homma, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2013-28 |
Our Two-Path Limited Speculation system PALS speculatively executes one of the top two paths of high frequency in loops.... [more] | CPSY2013-28 pp.109-114 |
| DC, CPSY (Joint) |
2013-08-02 18:00 |
Fukuoka | Kitakyushu-Kokusai-Kaigijyo | Consideration of Relation of Path Prediction and Branch Prediction in Loops Kazuhiro Kinkai, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba (Utunomiya Univ.) CPSY2013-29 |
We focus on Two-Path Limited Speculation method and evaluated path prediction accuracy with some path predictors. Pred... [more] |
CPSY2013-29 pp.115-120 |
| HIP | 2013-03-14 16:50 |
Okinawa | okinawa-sangyoushien center | A Development for an Object Driving System Using "Invisible Threads" Akira Fukushima, Katsuhito Akahane, Makoto Sato (Tokyo Inst. of Tech.) HIP2012-104 |
The aim of this research is moving real object on the tabletop display using the strings which is too thin to be apparen... [more] | HIP2012-104 pp.155-160 |
| VLD | 2013-03-05 14:55 |
Okinawa | Okinawa Seinen Kaikan | A Parallel Global Routing Method Sharing Routing Regions for Multi-Core Processors Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2012-150 |
Parallel routing methods using various parallel computing environments have been proposed in existing studies for reduci... [more] | VLD2012-150 pp.83-88 |
| DC, CPSY (Joint) |
2012-08-02 13:30 |
Tottori | Torigin Bunka Kaikan | Effect of Loop Unrolling for Two-Path Limited Speculation Method Yuki Homma, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2012-9 |
Our Two-Path Limited Speculation system PALS speculatively executes one of the top two paths of high frequency in loops.... [more] | CPSY2012-9 pp.1-6 |
| LQE, ED, CPM | 2011-11-17 10:55 |
Kyoto | Katsura Hall，Kyoto Univ. | Etch-pit method of threading dislocations in epitaxial AlN films Takuya Nomura, Hideto Miyake, Kazumasa Hiramatsu (Mie Univ.), Yuuki Ryu, Takaaki Kuwahara, Noriyuki Kuwano (Kyusyu Univ.) ED2011-75 CPM2011-124 LQE2011-98 |
AlN is an attractive substrate for short-wavelength optoelectronics devices based on AlGaN. We have investigated threadi... [more] | ED2011-75 CPM2011-124 LQE2011-98 pp.11-14 |
| CPSY | 2010-11-12 14:10 |
Okayama | Okayama Univ. | Evaluation of the S/W Scheduler for CMP Based on Continuation Model Hideaki Moriyama, Yoshinari Nomura, Hideo Taniguchi (Okayama Univ.) CPSY2010-27 |
In chip multi-processor based on the continuation concept, the hardware scheduler controls threads and achieves the high... [more] | CPSY2010-27 pp.11-16 |
| DC | 2009-12-11 14:50 |
Shimane | Transition and Trend of OS for Safety Control of Railway Signaling Hideo Nakamura (Nihon Univ.) DC2009-60 |
The single thread method OS is used for the software of a railway signaling failsafe computer system. It is because of R... [more] | DC2009-60 pp.25-29 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 11:20 |
Kochi | Kochi City Culture-Plaza | Proposal of Multi-Core Processor PALS to Realize Two-Path Limited Speculation Method Hiroyoshi Jutori, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2009-46 |
We have proposed a two-path limited speculation method for higher performance execution of program's loop. This method s... [more] | CPSY2009-46 pp.19-24 |
| CPSY | 2009-11-20 16:25 |
Kyoto | Campus Plaza Kyoto | A Method for CMP-oriented thread scheduling based on continuation model Hideaki Moriyama, Yoshinari Nomura, Hideo Taniguchi (Okayama Univ.) CPSY2009-41 |
Fuce processor is a variant of CMP processor, which has multiple thread execution cores. The computation model of the Fu... [more] | CPSY2009-41 pp.37-42 |
| SS | 2008-10-16 15:00 |
Yamanashi | University of Yamanashi, Kofu Campus | Thread Synchronization Using AspectJ Tomoyuki Uchikoshi, Yasuhiro Sugiyama (Nihon Univ) SS2008-30 |
We are trying to use the aspect-oriented technology to separate thread controlling mechanisms from application logics in... [more] | SS2008-30 pp.19-24 |
| IN | 2008-07-18 10:50 |
Hyogo | Koube Univ. | Implementing Real-time Control Services of Networked Home Appliances Masayuki Fukuda, Hiroshi Igaki, Masahide Nakamura (Kobe Univ.) IN2008-33 |
In this paper, we address a framework for building a new service for the home network system (HNS), called real-timeappl... [more] | IN2008-33 pp.41-46 |
| CPSY | 2005-12-16 14:25 |
Tochigi | Academia Hall, Utsunomiya Univ. | A Consideration and Evaluation of Thread Partitioning Method based on Program Structures Daisuke Mitsugi, Takahiko Kobayashi, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) |
We have studied a system that translates single-threaded codes to multithreaded ones at binary level. It is difficult to... [more] | CPSY2005-37 pp.25-30 |
| CPSY, VLD, IPSJ-SLDM | 2005-01-26 14:10 |
Kanagawa | Performance Evaluation of Speculative Thread Execution in the Single-Chip Multiprocessor SKY Akio Kamimurai, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada (Nagoya Univ.) |
We have proposed multi-processor architecture, called SKY, which efficiently executes multiple threads in parallel. In p... [more] | VLD2004-117 CPSY2004-83 pp.43-48 |
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