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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2015-08-05
14:30
Oita B-Con Plaza (Beppu) Efficient Thread Control Method for Parallel Loop Processing by Dynamic Binary Translation
Hiroyuki Obuchi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2015-29
In order to effectively utilize the performance of multicore processors spreading commonly at present, it is an importan... [more] CPSY2015-29
pp.155-160
ICD, CPSY 2014-12-01
15:15
Tokyo Kikai-Shinko-Kaikan Bldg. [Poster Presentation] A Study on a Comprehensive Architecture Exploration Environment for Emerging Applications
Shohei Takeuchi, Shinya Takamaeda Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST) ICD2014-77 CPSY2014-89
Emerging applications, such as graph processing and machine learning, contain several irregular memory access patterns a... [more] ICD2014-77 CPSY2014-89
pp.25-27
CPSY, DC
(Joint)
2014-07-28
18:15
Niigata Toki Messe, Niigata Performance Evaluation of Speculative Parallel Processing Utilizing Hardware Transactional Memory on Commercial Multi-core CPU
Yutaka Matsuno, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2014-16
Recently, it becomes essential to use parallel computation utilizing thread level parallelism as a method to utilize a s... [more] CPSY2014-16
pp.37-42
DC, CPSY
(Joint)
2013-08-02
14:30
Fukuoka Kitakyushu-Kokusai-Kaigijyo Reduction of Runtime Overhead in Automated Parallel Processing System using Valgrind
Takayuki Hoshi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2013-23
In order to efficiently utilize the performance of multicore processors, thread level parallel processing is indispensab... [more] CPSY2013-23
pp.79-84
ICD, IPSJ-ARC 2008-05-14
14:15
Tokyo   Performance Balancing: An Efficient Helper-Thread Execution on CMPs
Kenichi Imazato, Naoto Fukumoto, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
Conventional CMPs attempt to exploit the thread-level parallelism (TLP)
by using all of the cores integrated in a chip.... [more]
ICD2008-31
pp.75-80
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