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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 17 of 17  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2022-03-01
14:20
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
Evaluation of Efficiency for a Method to Locate High Power Consumption with Switching Provability
Ryu Hoshino, Taiki Utsunomiya, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2021-73
In recent years, as the high speed and miniaturization of LSIs have improved, it has become more difficult to test LSIs.... [more] DC2021-73
pp.51-56
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2020-11-17
10:30
Online Online Power Analysis Based on Probability Calculation of Small Regions in LSI
Ryo Oba, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32
Power consumption in LSI testing is higher than in functional mode since more switching activities occur. High power con... [more] VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32
pp.12-17
DC 2020-02-26
15:00
Tokyo   Improving Controllability of Signal Transitions in the High Switching Area of LSI
Jie Shi, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-94
Power consumption in LSI testing is larger than in functional mode. High power consumption causes excessive IR-drop and ... [more] DC2019-94
pp.49-54
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-14
16:35
Ehime Ehime Prefecture Gender Equality Center Test Generation for Hardware Trojan Detection Using the Delay Difference of a Pair of Independent Paths
Suguru Rikino, Yushiro Hiramoto, Satoshi Ohtake (Oita Univ.) VLD2019-46 DC2019-70
Hardware Trojan detection is important to ensure security of LSIs.
If a hardware Trojan is inserted in a signal line o... [more]
VLD2019-46 DC2019-70
pp.151-155
DC 2018-02-20
11:00
Tokyo Kikai-Shinko-Kaikan Bldg. Locating Hot Spots with Justification Techniques in a Layout Design
Yudai Kawano, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (Kyutech) DC2017-80
In general, power consumption during LSI testing is higher than functional operation. Excessive power consumption in at-... [more] DC2017-80
pp.19-24
R 2017-12-15
14:50
Tokyo Kikai-Shinko-Kaikan Bldg. Estimation of Headway considering Transition Interruption in Moving Block
Yoichi Sugiyama, Haruo Yamamoto, Iwata Koji (R.T.R.I.) R2017-58
A method of the train control which enables us to shorten a headway is necessary for early recovery and increase of the ... [more] R2017-58
pp.13-18
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-06
14:30
Kumamoto Kumamoto-Kenminkouryukan Parea A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST
Kyonosuke Watanabe, Satoshi Ohtake (Oita Univ.) VLD2017-35 DC2017-41
With the miniaturization and high speed of large scale integrated circuits, it has become important to test delay faults... [more] VLD2017-35 DC2017-41
pp.49-54
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-01
14:40
Nagasaki Nagasaki Kinro Fukushi Kaikan On discrimination method of a resistive open using delay variation induced by signal transitions on adjacent lines
Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) VLD2015-42 DC2015-38
The effect of a resistive open results in small delay in an IC. It is difficult to test small delay since signal delay a... [more] VLD2015-42 DC2015-38
pp.31-36
DC 2015-06-16
15:00
Tokyo Kikai-Shinko-Kaikan Bldg. A Method to Identify High Test Power Areas in Layout Design
Kohei Miyase (Kyutech), Matthias Sauer, Bernd Becker (Univ. Freiburg), Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2015-18
The problems related to power consumption during at-speed testing is becoming more serious. Particularly, excessive peak... [more] DC2015-18
pp.13-18
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-29
09:45
Kagoshima   A Method of High Quality Transition Test Generation Using RTL Information
Hiroyuki Nakashima, Satoshi Ohtake (Oita Univ.) VLD2013-94 DC2013-60
With the miniaturization and high speed of large scale integrated circuits (VLSIs), it has become important to test dela... [more] VLD2013-94 DC2013-60
pp.239-244
DC 2012-06-22
13:00
Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg An evaluation of a don't care filling method to improve fault sensitization coverage
Ryosuke Wakasugi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyusyu Univ) DC2012-9
A single stuck-at fault model and a transition fault model have been widely used to generate test patterns for VLSIs. Ho... [more] DC2012-9
pp.1-6
DC 2012-02-13
11:05
Tokyo Kikai-Shinko-Kaikan Bldg. Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test
Hiroaki Tanaka, Kohei Miyase, Kazunari Enokimoto, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2011-78
In this paper, we present to generate a test vector set to detect both transition and path delay faults. The proposed me... [more] DC2011-78
pp.13-18
DC 2012-02-13
14:25
Tokyo Kikai-Shinko-Kaikan Bldg. A method to reduce the number of test patterns for transition faults using control point insertions
Akihiko Takahashi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ) DC2011-82
In recent year, the growing density and complexity for VLSIs cause an increase in the number of test patterns. Moreover,... [more] DC2011-82
pp.37-42
DC 2011-02-14
11:00
Tokyo Kikai-Shinko-Kaikan Bldg. An Analysis of Critical Paths for Field Testing with Process Variation Consideration
Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushuu Univ) DC2010-61
Recently, it has the problem that good VLSIs in production testing become defective VLSIs in the fields because small de... [more] DC2010-61
pp.13-19
DC 2010-02-15
13:45
Tokyo Kikai-Shinko-Kaikan Bldg. A Test Compaction Oriented Control Point Insertion Method for Transition Faults
Yoshitaka Yumoto, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.) DC2009-72
The recent advances in semiconductor processing technology have resulted in the exponential increase in LSI circuit dens... [more] DC2009-72
pp.45-50
DC 2010-02-15
14:10
Tokyo Kikai-Shinko-Kaikan Bldg. On Calculation of Delay Test Quality for Test Cubes and X-filling
Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech./JTS) DC2009-73
This paper proposes a method to compute delay values in 3-valued fault simulation for test cubes which are test patterns... [more] DC2009-73
pp.51-56
DC 2008-02-08
09:50
Tokyo Kikai-Shinko-Kaikan Bldg. Diagnostic Test Generation for Transition Faults
Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Toru Kikkawa, Yuzo Takamatsu (Ehime Univ.) DC2007-69
In modern manufacturing technologies with the shrinking of manufacturing process,
LSIs may have several metal intercon... [more]
DC2007-69
pp.13-18
 Results 1 - 17 of 17  /   
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