IEICE Technical Report

Print edition: ISSN 0913-5685
Online edition: ISSN 2432-6380

vol. 105, no. 148

VLSI Design Technologies

Workshop Date : 2005-06-28 / Issue Date : 2005-06-21

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VLD2005-26
Development of All-weather Realtime Player Tracing System by Adaptive Background Renewal
Munehiro Tokikura, Akinori Nishihara (TIT)
pp. 1 - 6

VLD2005-27
High Accuracy Motion Estimation for Video Sequences Based on Phase-Only Correlation
Norihito Numa, Loy Hui Chien, Takafumi Aoki (Tohoku Univ.), Satoshi Kondo (Matsushita Electric Industrial Co., Ltd.)
pp. 7 - 12

VLD2005-28
Fast Image Identification for Coded Images with Different Compression Ratio
Ikue Iizuka, Fitri Arnia, Masaaki Fujiyoshi, Hitoshi Kiya (Tokyo Metro. Univ.)
pp. 13 - 18

VLD2005-29
A Scale Estimation Algorithm Based on Phase-Only Correlation for Electron Microscope Images
Sei Nagashima, Takafumi Aoki (Tohoku Univ.), Ruriko Tsuneta (Hitachi, Ltd., Central Reserch Laboratry)
pp. 19 - 24

VLD2005-30
A compiler framework to combine multiple code optimization methods
Yuhei Kaneko, Nobuhiko Sugino (Tokyo Institute of Tech.)
pp. 25 - 29

VLD2005-31
Optimal Design of Limited Carry-Propagation Adders Based on Redundant Number Systems
Naofumi Homma, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Tohtech)
pp. 31 - 36

VLD2005-32
Formal Design of Arithmetic Circuits with Arithmetic Description Language: ARITH
Yuki Watanabe, Naofumi Homma, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Tohtech)
pp. 37 - 42

VLD2005-33
A Memory-Reduction Method for Partially-Parallel LDPC Decoder Based on Min-Sum Algorithm
Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.)
pp. 43 - 48

VLD2005-34
High Driving Capability by Lateral Unified CBiCMOS Inverter with Resister-Ratio Type Control Circuits
Takashi Hamahata, Toshiro Akino (Kinki Univ.)
pp. 49 - 54

VLD2005-35
Design and Evaluation of a Bit-Parallel Magnitude-Comparison CAM Based on TMR Logic
Kohei Shoji, Takahiro Hanyu (Tohoku Univ.)
pp. 55 - 59

VLD2005-36
Complementary Ferroelectric Capacitor Logic and its Application to Fully Parallel Arithmetic VLSI
Shoun Matsunaga, Takahiro Hanyu (Tohoku Univ.)
pp. 61 - 65


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan