Print edition: ISSN 0913-5685
Online edition: ISSN 2432-6380
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IE2005-79
A Phase Noise Minimization of CMOS LC-VCOs Over Wide Tuning Range and Large PVT Variations
Daisuke Miyashita, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Kenichi Agawa, Mototsugu Hamada (Toshiba Corp.)
pp. 1 - 5
IE2005-80
Substrate Noise Reduction and Random Variability Neutralization with Self Adjusted Forward Body Bias Control
Yoshihide Komatsu, Koichiro Ishibashi, Toshiro Tsukada, Masaharu Yamamoto (STARC), Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata (Kobe Univ.)
pp. 7 - 12
IE2005-81
Thermal Analysis on Microprocessors
Naoyuki Hasegawa, Mutsuo Ito, Ryusuke Egawa, Kenichi Suzuki, Tadao Nakamura (Tohoku Univ.)
pp. 13 - 18
IE2005-82
Development of an embedded processor core SH-X2
Takashi Okada (Hitachi), Tomoichi Hayashi, Takehiro Shimizu (Renesas), Fumio Arakawa, Tetsuya Yamada (Hitachi), Osamu Nishii, Toshihiro Hattori (Renesas)
pp. 19 - 24
IE2005-83
Single-Chip Multi-Processor Integrating Quadruple 8-Way VLIW Processors
Atsushi Tanaka, Atsuhiro Suga, Fumihiko Hayakawa, Shinichiro Tago, Satoshi Imai (Fujitsu Lab)
pp. 25 - 29
IE2005-84
Compaction of Arithmetic Unit with Bit-Level-Parallelism
Jubee Tada (Yamagata Univ.), Ryusuke Egawa (Tohoku Univ.), Gensuke Goto (Yamagata Univ.), Tadao Nakamura (Tohoku Univ.)
pp. 31 - 35
IE2005-85
[Invited Talk]
Development of Image Recognition Processor Based on Configurable Processor
Takashi Miyamori (Toshiba)
pp. 37 - 42
IE2005-86
[Invited Talk]
Technology for Embedded Processors
Kunio Uchiyama (Hitachi)
pp. 43 - 47
IE2005-87
A Reliability Evaluation Technique for Soft-Error Susceptible Computer Systems
Makoto Sugihara (ISIT), Tohru Ishihara (Kyushu Univ.), Koji Hashimoto (Fukuoka Univ.), Masanori Muroyama (Kyushu Univ.)
pp. 49 - 54
IE2005-88
A study for hardware optimization using a high level synthesis fron C
Satoru Inoue, Tsuyoshi Kondo, Tomonori Izumi, Masahiro Fukui (Rits)
pp. 55 - 60
IE2005-89
A Cache-Defect-Aware Code Placement Technique for Improving the Performance of Processor
Tohru Ishihara (Kyushu Univ.), Farzan Fallah (FLA)
pp. 61 - 66
IE2005-90
A study for power and speed tradeoff estimation for behavior hardware model
Noriyuki Inoue, Katsuhiro Oshikawa, Tomonori Izumi, Masahiro Fukui (Rits Univ.)
pp. 67 - 72
IE2005-91
A Monitor Generation Method for Formal Monitor-based Verification Considering Input Constraints
Yosuke Kakiuchi (Osaka Univ.), Akira Kitajima (Osaka Electro-Communication Univ.), Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.)
pp. 73 - 78
IE2005-92
A cell library development methodology for character projection
Makoto Sugihara (ISIT), Taiga Takata, Kenta Nakamura (Kyushu Univ.), Ryoichi Inanami (e-BEAM), Hiroaki Hayashi (Tokyo Electron), Katsumi Kishimoto (e-BEAM), Tetsuya Hasebe (Tokyo Electron), Yukihiro Kawano (e-BEAM), Yusuke Matsunaga, Kazuaki Murakami (Kyushu Univ.), Katsuya Okumura (Univ. of Tokyo)
pp. 79 - 84
IE2005-93
A Study for Power Grid Optimization
Taiki Harada, Kenji Kusano, Takayuki Shimada, Hironobu Ishijima, Masahiro Fukui (Rits Univ.)
pp. 85 - 90