Print edition: ISSN 0913-5685
Online edition: ISSN 2432-6380
[TOP] | [2006] | [2007] | [2008] | [2009] | [2010] | [2011] | [2012] | [Japanese] / [English]
DC2005-31
[Fellow Memorial Lecture]
Layout CAD and DFM
-- Beginning and Maturity --
Takashi Mitsuhashi (Cadence Japan)
pp. 1 - 6
DC2005-32
40-Gbps 4:1 MUX/1:4 DEMUX in 90-nm standard CMOS technology
Kouichi Kanda, Daisuke Yamazaki, Takuji Yamamoto, Minoru Horinaka, Junji Ogawa, Hirotaka Tamura, Hiroyuki Onodera (Fujitsu Labs.)
pp. 7 - 14
DC2005-33
Enhancement of an Angular Position Error Measurement Circuit for Rotary Encoders
Teruo Tamama, , Tadashi Masuda (SIST)
pp. 15 - 20
DC2005-34
Low Power Design for IEEE 802.11 WLAN at the Medium Access Control Layer
EL Bourichi Adil, Hiroto Yasuura (Kyushu Univ.)
pp. 21 - 24
DC2005-35
Logic Synthesis Technique for High Speed Dynamic Logic with Asymmetric Slope Transition
Masao Morimoto, Makoto Nagata (Kobe Univ.), Kazuo Taki
pp. 25 - 30
DC2005-36
A Discussion about Timing Signal Design Considering Delay Variation
Masashi Imai, Kouichi Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo)
pp. 31 - 36
DC2005-37
Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation
Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo)
pp. 37 - 42