IEICE Technical Report

Print edition: ISSN 0913-5685
Online edition: ISSN 2432-6380

vol. 105, no. 504

Circuits and Systems

Workshop Date : 2006-01-13 / Issue Date : 2006-01-06

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CAS2005-87
A Consideration for High Gain of Even-Harmonic Mixers
Toshio Ide, Takayuki Matuura, Koichi Tanno, Takako Toyama (Miyazaki Univ.)
pp. 1 - 6

CAS2005-88
Examination of FG-MOS Multivalued SRAM
Hiroyasu Kondou, Youhei Ishikawa, Sumio Fukai (Saga University)
pp. 7 - 11

CAS2005-89
Characteristics Improvement of PLLs Using Phase Interpolation -- Circuit Optimization of Phase Interpolation --
Manabu Inoue, Fuminori Kobayashi, Minoru Watanabe (KIT)
pp. 13 - 17

CAS2005-90
Composition of Sequential Circuit Method Multipliers using Multiple-Valued
Naohiro Nomura, Noriaki Muranaka (Kansai Univ.), Shigeru Imanishi (Kobe Institute of Computing/College of Information Technology), Masataka Tokumaru (Kansai Univ.)
pp. 19 - 24

CAS2005-91
Length and width of segmental transmission line optimization using GA
Naoki Koizumi, Ikuo Yoshihara, Kunihito Yamamori (Univ. of Miyazaki), Moritoshi Yasunaga (Univ. of Tsukuba)
pp. 25 - 30

CAS2005-92
Simultaneous Control-step and Skew Assignment for Control Signals in RT-Level Datapath Synthesis
Takayuki Obata, Mineo Kaneko (JAIST)
pp. 31 - 36

CAS2005-93
Resource Sharing in Dual-Rail Two-Phase Asynchronous Datapath Synthesis
Koji Ohashi, Mineo Kaneko (JAIST)
pp. 37 - 42

CAS2005-94
A Transduction-based Framework to Synthesize RSFQ Circuits
Shigeru Yamashita (NAIST), Katsunori Tanaka (NEC), Hideyuki Takada (Kyoto Univ.), Koji Obata, Kazuyoshi Takagi (Nagoya Univ.)
pp. 43 - 48

CAS2005-95
Budget Free Hierarchical Design
Yuichi Nakamura (NEC), Mitsuru Tagata (HNES)
pp. 49 - 54


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