Print edition: ISSN 0913-5685
Online edition: ISSN 2432-6380
[TOP] | [2006] | [2007] | [2008] | [2009] | [2010] | [2011] | [2012] | [Japanese] / [English]
VLD2005-122
Low Power Design of System LSI in the Presence of Leakage Current of MOSFET
Shigeyoshi Watanabe (Shonan Inst. of Tech.)
pp. 1 - 6
VLD2005-123
A design platform for battery drived lowpower systems
Tatsuya Koyagi, Hiroyoshi Hirai, Chihiro Mori, Masahiro Fukui (Rits)
pp. 7 - 12
VLD2005-124
A proposal for modeling the battery life time for battery drived systems
Chihiro Mori, Tatsuya Koyagi, Masahiro Fukui (Rits)
pp. 13 - 18
VLD2005-125
A simulation technique of dynamic power supply / ground noise in large-scale digital LSIs
Toshifumi Uemura, Makoto Nagata (Kobe Univ)
pp. 19 - 24
VLD2005-126
[Invited Talk]
Digital Photo Albuming using Descriptive Metadata
-- MPEG-7 Signal characteristic description tools for MPEG-A Photo Player --
Akio Yamada (NEC)
pp. 25 - 30
VLD2005-127
A Fault Tolerant LUT Cascade Emulator
Hiroki Nakahara, Tsutomu Sasao (K.I.T)
pp. 31 - 36
VLD2005-128
A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Technology
Teruhito Tanaka, Kouji Hatada, Tetsuya Konishi, Yoshikazu Odajima, Takashi Kambe (Kinki Univ.)
pp. 37 - 42
VLD2005-129
Coarse-grained Reconfigurable Hardware with Mapping Mechanisms of Floating Point Operations and Chained Additions
Hidemi Akutsu, Shinji Kimura (Waseda Univ.)
pp. 43 - 48
VLD2005-130
A reconfigurable circuit to utilize and compensate device variations
Manabu Kotani, Kazuya Katsuki, Kosuke Ogata, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.)
pp. 49 - 54
VLD2005-131
Transistor sizing for LCD driver circuit under constraint of charged pixel voltage
Takahito Ijichi, Masanori Hashimoto (Osaka Univ.), Shingo Takahashi, Shuji Tsukiyama (Chuo Univ.), Isao Shirakawa (Univ. of Hyogo)
pp. 55 - 60
VLD2005-132
An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design
Takayuki Gyohten, Fukashi Morishita (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.)
pp. 61 - 66
VLD2005-133
Impact of Three-Dimensional Transistor on the pattern area reduction for ULSI
Shigeyoshi Watanabe (Shonan Inst. of Tech.)
pp. 67 - 72