IEICE Technical Report

Print edition: ISSN 0913-5685

Neurocomputing

Workshop Date : 2006-11-11 / Issue Date : 2006-11-04

NC2006-63
Investigation of a switched resistor network to develop a silicon retina
Seiji Kameda, Shosuke Morimoto, Atsushi Iwata (Hiroshima Univ.)
pp. 1 - 6

NC2006-64
Pulse-type Hardware Model of an Input Region in a Visual Cortex
Takaaki Iwamoto, Yoshifumi Sekine (Nihon Univ.)
pp. 7 - 12

NC2006-65
A VLSI-Implementation-Friendly Ego-Motion Detection Algorithem Based on Edge-Histogram Matching
Jia Hao, Tadashi Shibata (Univ. of Tokyo)
pp. 13 - 17

NC2006-66
K-means VLSI Processor and its application to autonomous area segregation in images
Shigetaka Morikawa, Kiyoto Ito, Tadashi Shibata (Tokyo Univ.)
pp. 19 - 24

NC2006-67
[Invited Talk] A VLSI brain processor system mimicking the processing in mind -- Building real-time visual perception systems --
Tadashi Shibata (Univ. of Tokyo)
pp. 25 - 33

NC2006-68
Bifurcation phenomena from an artificial spiking neuron with piecewise-linear base signal
Toshimitsu Ohtani, Toshimichi Saito, Hiroyuki Torikai (Hosei Univ.)
pp. 35 - 39

NC2006-69
An approach toward learning algorithm for Digital Spiking Neuron
Hiroyuki Torikai, Toshimichi Saito (Hosei Univ.)
pp. 41 - 46

NC2006-70
Research on Four Valued T-Gate with νMOSFETs
Yoshikazu Ishimaru, Hiroyasu Kondou (Saga Univ), Yohei Ishikawa (Ariake NCT), Sumio Fukai (Saga Univ)
pp. 47 - 50

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan