IEICE Technical Report

Print edition: ISSN 0913-5685

Circuits and Systems

Workshop Date : 2006-11-21 / Issue Date : 2006-11-14

CAS2006-55
Computational Evaluation of Heuristic Algorithms for a Share Transfer Problem
Toshiyuki Miyamoto, Sadatoshi Kumagai (Osaka Univ.)
pp. 1 - 6

CAS2006-56
Performance Evaluation of Workflows Using Continuous Approximation
Kunihiko Hiraishi (JAIST)
pp. 7 - 12

CAS2006-57
A Visual Trace Tool of Graph Algorithms Providing Hierarchical View of Graphs
Kazuya Sakamoto, Masahiro Yamauchi (Kinki Univ.), Toshimasa Watanabe (Hiroshima Univ.)
pp. 13 - 18

CAS2006-58
[Invited Talk] Dynamic Re-configurable Architecture PCA for Stream Processing
Kiyoshi Oguri (Nagasaki Univ.)
pp. 19 - 24

CAS2006-59
Solution Space Reduction of Sequence-Pair using Quadratic Wire Length Minimization
Yuuki Yano, Mineo Kaneko (JAIST)
pp. 25 - 30

CAS2006-60
An Improvement Method of the Budget Free Design Method for 100M Tr. Circuits
Yuichi Nakamura (NEC), Mitsuru Tagata (HNES)
pp. 31 - 35

CAS2006-61
The Complexity of Three-Dimensional Channel Routing
Satoshi Tayu, Shuichi Ueno (Tokyo Inst. of Tech.)
pp. 37 - 41

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan