IEICE Technical Report

Print edition: ISSN 0913-5685

Reconfigurable Systems

Workshop Date : 2006-11-30 / Issue Date : 2006-11-23

RECONF2006-44
A Design of AES S-BOX circuit for DPA countermeasure
Minoru Sasaki, Keisuke Iwai, Takakazu Kurokawa (NDA.)
pp. 1 - 6

RECONF2006-45
Development and evaluation of virus check system using FPGA
Yukari Ishida (Toho Univ.), Yosuke Iijima (Univ.of Tsukuba), Eiichi Takahashi (AIST), Tatsumi Furuya (Toho Univ.), Tetsuya Higuchi (AIST)
pp. 7 - 12

RECONF2006-46
A template matching circuit using with hwObjects including reconfigurable processing circuits.
Rika Sato, Kenji Kudo, Masatoshi Sekine (TUAT)
pp. 13 - 18

RECONF2006-47
Design of Radix Converters Using Arithmetic Decomposition (2)
Yukihiro Iguchi (Meiji Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT)
pp. 19 - 24

RECONF2006-48
Architecture for numerical function generators using EVBDDs
Shinobu Nagayama (Hiroshima City Univ.), Tsutomu Sasao (K.I.T), Jon T. Butler (Naval Postgraduate School)
pp. 25 - 30

RECONF2006-49
Consideration about Reconfigurable Architecture based on Digit Serial Arithmetics
Kazuya Tanigawa, Tetsuo Hironaka (Hirhoshima City Univ.)
pp. 31 - 36

RECONF2006-50
A Low-Power Technique using Resource Sharing Approach for Multi-Context Device
Hideaki Monji, Hiroshi Shinohara, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 37 - 42

RECONF2006-51
Area-Efficient Reconfigurable Architecture for Media Processing
Kazuma Takahashi, Yukio Mitsuyama, Takao Onoye (Osaka Univ.), Isao Shirakawa (Univ. of Hyogo)
pp. 43 - 48

RECONF2006-52
Performance Evaluation of Multi-core DRP for Stream Application
Naohiro Katsura, Yohei Hasegawa, Vu Manh Tuan, Hiroki Matsutani, Hideharu Amano (Keio Univ.)
pp. 49 - 54

RECONF2006-53
Development of Benchmark Test for comparing Dynamic Reconfigurable Architecture
Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (HCU)
pp. 55 - 60

RECONF2006-54
An example of function sharing implementation for reconfigurable systems
Hideaki Yoshihiro, Takeru Kisanuki, Taiichiro Yatsunami, Yukinobu Kiyota, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto City Univ.)
pp. 61 - 66

RECONF2006-55
Delay optimized technology mapping for Variable Grain Logic Cell
Hideaki Nakayama, Ryoichi Yamaguchi, Motoki Amagasaki, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 67 - 72

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan