IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Computer Systems

Workshop Date : 2007-04-20 / Issue Date : 2007-04-13

CPSY2007-1
Soft Error Hardend Latch Scheme for Enhanced Scan Based Delay Fault Testing
Takashi Ikeda, Kazuteru Namba, Hideo Ito (Chiba Univ.)
pp. 1 - 6

CPSY2007-2
A scheduling algorithm in high-level synthesis for soft error tolerance with chained operations
Shintaro Imamura, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 7 - 12

CPSY2007-3
Building Time-Stamping Grid and Basic Experiment
Takeshi Nishikawa, Satoshi Matsuoka (Tokyo Tech)
pp. 13 - 18

CPSY2007-4
Performance Improvement of Network Filtering on TwinOS
Yoshinari Nomura, Yuuma Yamamoto, Hideo Taniguchi (Okayama Univ.)
pp. 19 - 24

CPSY2007-5
[Invited Talk] Trends and Future Problems of IT Systems High Availablity -- From Mainframes to Open Systems --
Toru Shonai (Hitachi)
pp. 25 - 30

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan