IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

VLSI Design Technologies

Workshop Date : 2007-11-22 / Issue Date : 2007-11-15

VLD2007-89
Comparison between STA and SSTA results in microprocessor design
Noriyuki Ito, Hiroaki Komatsu, Hiroyuki Sugiyama, Naomi Bizen, Katsumi Iguchi, Yuji Yoshida (Fujitsu)
pp. 1 - 6

VLD2007-90
A New Technique for Elimination of Irregular Data in Measured Values -- A Data Screening Technique Appling Skewness of Basic Statistic --
Shin-ichi Ohkawa, Hiroo Masuda (Renesas)
pp. 7 - 12

VLD2007-91
A Study of Grid-Based Modeling of Spatially Correlated Manufacturing Variability for SSTA
Shinyu Ninomiya, Masanori Hashimoto (Osaka Univ.)
pp. 13 - 17

VLD2007-92
Highly Extensible Base Processors for Short-term ASIP Design
Hirofumi Iwato, Takuji Hieda, Hiroaki Tanaka (Osaka Univ.), Jun Sato (Tsuruoka NCT), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
pp. 19 - 24

VLD2007-93
Complexities and Algorithms of Minimum-Delay Compensation Problems in Datapath Synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST)
pp. 25 - 30

VLD2007-94
A Schedule Improvement with Skew Control in Datapath Synthesis
Takayuki Obata, Mineo Kaneko (JAIST)
pp. 31 - 36

VLD2007-95
Necessary and Sufficient Conditions for Symmetry Placements
Kunihiro Fujiyoshi, Chikaaki Kodama, Shinichi Koda (TUAT)
pp. 37 - 41

VLD2007-96
Improved Method of Rectilinear Block Packing Based on O-Tree Representation
Hidehiko Ukibe, Kunihiro Fujiyoshi (TUAT)
pp. 43 - 48

VLD2007-97
Parallel prefix adder synthesis based on Ling’s carry computation
Taeko Matsunaga, Shinji Kimura (Waseda Univ.), Yusuke Matsunaga (Kyushu Univ.)
pp. 49 - 54

VLD2007-98
An Efficient Behavioral Synthesis Method Considering Specialized Functional Units
Tsuyoshi Sadakata, Yusuke Matsunaga (Kyushu Univ.)
pp. 55 - 60

VLD2007-99
A Hardware Engine for Generation Deformed Map
Akira Arahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 61 - 66

VLD2007-100
An LDPC Decoder Based on the Min-Sum Algorithm for High Speed WLAN Systems
Nozomu Hama, Hiroyuki Shimajiri, Takeo Yoshida (Univ. of the Ryukyus)
pp. 67 - 72

VLD2007-101
Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs
Taiga Takata, Yusuke Matsunaga (Kyushu Univ.)
pp. 73 - 78

VLD2007-102
Cycle Partitioned Scheduling for Code Optimization of VLIW DSP
Yuuki Masui, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 79 - 84

VLD2007-103
Retargetable Linear Assembler for VLIW Processor
Satoshi Nogaito, Nagisa Ishiura (Kwansei Gakuin Univ.), Masaharu Imai (Osaka Univ.)
pp. 85 - 90

VLD2007-104
Memory Assignment Method Considering Orders of Operands for Massively Parallel Fine-grained SIMD Processor
Akira Kobashi, Ittetsu Taniguchi, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas)
pp. 91 - 96

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan