Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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RECONF2008-1
A Study of a Fault-Tolerant System using Partial Reconfiguration
Atsuhiro Kanamaru, Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga (Tsukuba Univ.)
pp. 1 - 6
RECONF2008-2
An Implementation of High Precision Floating-point Operation Units on FPGA
Naohito Nakasato (Univ. Aizu), Tadashi Ishikawa (KEK)
pp. 7 - 12
RECONF2008-3
Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems
Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda (AIST)
pp. 13 - 18
RECONF2008-4
FPGA Implementation of Elliptic Curve Arithmetic in Characteristic Five by High-level Synthesis
YoungKwang Moon (Tokyo Univ.), Hideyuki Tsuchiya, Yuichiro Shibata, Ryuichi Harasawa, Kiyoshi Oguri (Nagasaki Univ.)
pp. 19 - 24
RECONF2008-5
Development of Compiler for Dynamic Reconfigurable Architecture DS-HIE which Adopts Digit-serial Computation
Yasuhiro Nishinaga, Takuro Uchida, Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)
pp. 25 - 30
RECONF2008-6
Path Planning Method for MIMD Controlled data communication in MX Core
Akihiro Kodama, Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (kumamoto Univ.)
pp. 31 - 36
RECONF2008-7
A Link Removal Methodology for Application-Specific Networks-on-chip on FPGAs
Daihan Wang (Keio Univ./JST), Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII/JST), Hideharu Amano (Keio Univ.)
pp. 37 - 42
RECONF2008-8
A Novel Cluster Structure for Variable Grain Logic Cell
Kazuki Inoue, Kazunori Matsuyama, Yoshiaki Satou, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 43 - 48
RECONF2008-9
[Invited Talk]
RadidMatriX: 2D Array Processor for Algebraic Path Problem
Toshiaki Miyazaki (Univ. of Aizu)
pp. 49 - 54
RECONF2008-10
Designing And Evaluating Dynamically Reconfigurable Processor with Power Gating Technique
Yoshiki Saito (Keio Univ.), Toshiaki Shirai (Shibaura Inst.), Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi (Keio Univ.), Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami (Shibaura Inst.), Hideharu Amano (Keio Univ.)
pp. 55 - 60
RECONF2008-11
A multi-context dynamic optically reconfigurable gate array using a silver-halide holographic memory
Daisaku Seto, Minoru Watanabe (Shizuoka Univ.)
pp. 61 - 64
RECONF2008-12
Fast optical reconfigurations of four-contexts ORGAs
Mao Nakajima, Minoru Watanabe (Shizuoka Univ.)
pp. 65 - 70
RECONF2008-13
Feature Extraction from Stereo Images by FPGA-Based Stream Processing
Shinsuke Nino, Hidenori Matsubayashi, Yuichiro Shibata, Tsuyoshi Hamada, Kiyoshi Oguri (Nagasaki Univ.)
pp. 71 - 76
RECONF2008-14
An Approach for Downscaling Images for Real-time Pattern Detection
Yoshifumi Tanida, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 77 - 82
RECONF2008-15
How fast is an FPGA in image processing ?
Takashi Saegusa, Tsutomu Maruyama, Yoshiki Yamaguchi (Univ. of Tsukuba)
pp. 83 - 88
RECONF2008-16
An implementation of a watershed algorithm based on connected components on FPGA
Dang Ba Khac Trieu, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 89 - 94
RECONF2008-17
Implementation and Evaluation of OS Functions for a Computer System Having FPGA Devices
Kazuya Tokunaga, Akira Kojima, Tetsuo Hironaka (Hiroshima City Univ)
pp. 95 - 100
RECONF2008-18
Context Virtualization Techniques for Dynamically Reconfigurable Hardware
Takeshi Inuo, Kengo Nishino, Nobuki Kajihara (NEC)
pp. 101 - 106
RECONF2008-19
Context Virtualization mechanism for Dynamically Reconfigurable Hardware
Kengo Nishino, Takeshi Inuo, Nobuki Kajihara (NEC)
pp. 107 - 112
RECONF2008-20
Pipeline Scheduling with Input Port Constraints for an FPGA-based Biochemical Simulator
Tomoya Ishimori, Hideki Yamada, Yuichiro Shibata (Nagasaki Univ.), Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi (Keio Univ.), Noriko Hiroi (EMPL-EBI), Kiyoshi Oguri (Nagasaki Univ.)
pp. 113 - 118
RECONF2008-21
Implementation and Evaluation of an Efficient Fluid Analysis System on Multiple FPGAs
Hirokazu Morishita, Yasunori Osana (Keio Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.)
pp. 119 - 124
RECONF2008-22
Design and Implementation of Viterbi Decoder for Multi-Constraint Length Using Reconfigurable Processor
Yuken Kishimoto, Shinichiro Haruyama, Masao Nakagawa, Hideharu Amano (Keio Univ.)
pp. 125 - 130
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.