IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 112, Number 248

Image Engineering

Workshop Date : 2012-10-18 - 2012-10-19 / Issue Date : 2012-10-11

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Table of contents

IE2012-64
Human Behavior Detection Using Direction Change Invariant Features of Cubic Higher Order Local Auto Correlation
Takeyuki Ishii, Hitomi Murakami, Atsushi Koike (Seikei Univ.)
pp. 1 - 6

IE2012-65
Avoiding Error Magnification in Weighted Median Cut Quantization in Decoding Process -- High Quality Data Compression of Sparse Histogram Images --
Toru Ikarashi, Masahiro Iwahashi (Nagaoka Univ. of Tech.), Hitoshi Kiya (Tokyo Metropolitan Univ.)
pp. 7 - 12

IE2012-66
A Design of Hilbert Transformers using an L1 error criterion
Ikuya Murakami, Naoyuki Aikawa (Tokyo Univ. of Science)
pp. 13 - 18

IE2012-67
A 16-gray-scale image recognition on a dynamically reconfigurable vision architecture
Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito (Shizuoka Univ.)
pp. 19 - 23

IE2012-68
Learning of shade for beginners based on interactive pencil-drawing learning support system using tablet PC
Akihiro Sawada, Masashi Kameda (Iwate City Univ.)
pp. 25 - 30

IE2012-69
[Invited Talk] Computing Technologies for Human-Centered Real-World Intelligent Systems
Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
pp. 31 - 33

IE2012-70
Power consumption analysis of a mono instruction set computer architecture
Hiroyuki Ito, Minoru Watanabe (Shizuoka Univ.)
pp. 35 - 38

IE2012-71
Design of a Packet-Transfer-Based Dynamic Reconfigurable VLSI Processor for Reduction of a Configuration Memory Size
Yoshichika Fujioka (Hachinohe Inst. of Tech.), Michitaka Kameyama (Tohoku Univ.)
pp. 39 - 44

IE2012-72
Design of Stochastic Flash A/D Converter using a non-linearity calibration technique
Shinya Yano, Hyunju Ham, Toshimasa Matsuoka, Jun Wang, Ikkyun Jo (Osaka Univ.)
pp. 45 - 48

IE2012-73
A 9-bit 10MSps SAR ADC with Double Input Range for Supply Voltage
Gong Chen, Yu Zhang, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang, Jing Li (Design Algorithm Lab.)
pp. 49 - 53

IE2012-74
[Invited Talk] Development of Heterogeneous Multi-Core SoC ViscontiTM2 for Image Recognition Applications
Takashi Miyamori, Yasuki Tanabe, Moriyasu Banno (Toshiba)
pp. 55 - 58

IE2012-75
Accelerator Architecture for Multi Scale Filter Operation
Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
pp. 59 - 64

IE2012-76
Load buffer with conversion capability from tiled data to raster data for motion search
Takumi Inomata, Atsushi Tachino, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ.)
pp. 65 - 70

IE2012-77
A Low Power CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling (DVFS) and Adaptively Assigned Breaking-off Condition (A2BC) Motion Estimation Algorithm
Tadayoshi Enomoto, Nobuaki Kobayashi (Chuo Univ)
pp. 71 - 76

IE2012-78
CMOS Op-amp Circuit Synthesis with Geometric Programming
Yu Zhang, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang, Jing Li (Design Algorithm Lab.)
pp. 77 - 82

IE2012-79
Fast Estimation of Dynamic Delay Distribution
Dai Akita, Kenta Ando (Osaka Univ.), Atsushi Takahashi (Tokyo Tech.)
pp. 83 - 88

IE2012-80
Reduction of array accesses with WAR dependencies
Takayuki Ookawa, Kenshu Seto (Tokyo City Univ.)
pp. 89 - 94

IE2012-81
Secure Scan Architecture Using State Dependent Scan Flip-Flop with Key-Based Configuration on RSA Circuit  
Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 95 - 100

IE2012-82
Write Reduction for Non-volatile Registers Using the Max-flow Min-cut Theorem
Yudai Itoi, Shinji Kimura (Waseda Univ.)
pp. 101 - 106

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan