IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Reconfigurable Systems

Workshop Date : 2015-09-18 - 2015-09-19 / Issue Date : 2015-09-11

RECONF2015-32
A Design of Basic Functions and Forced Play of TRAX Game for FPGA with High-Level Synthesis Tool
Tomonori Izumi, Masashi Ono, Yuuya Hiroe, Lin Meng (Ritsumeikan Univ.)
pp. 1 - 6

RECONF2015-33
Trax solver based on machine-learned evaluation function
Takuya Nakamichi, Yusuke Sonoda, Takayuki Matsuzaki, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 7 - 12

RECONF2015-34
Comparison of machine learning classifiers for HOG-based human detection on an FPGA
Masahito Oishi, Yoshiki Hayashida, Ryo Fujita, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 13 - 18

RECONF2015-35
[Invited Talk] Game Tree Search Techniques and its Application to Computer Shogi
Shogo Takeuchi (Hokkaido Univ.)
p. 19

RECONF2015-36
A High-level Hardware Design Environment in Python
Shinya Takamaeda (NAIST)
pp. 21 - 26

RECONF2015-37
Design of Hardware Description Language FSL Based on Object-Oriented/Functional Programming Languages
Nobuya Watanabe, Akira Nagoya (Okayama Univ.)
pp. 27 - 32

RECONF2015-38
Empirical evaluation of an arithmetic design approach with diversity and redundancy for FPGAs
Yudai Shirakura, Kenichi Morimoto (Nagasaki Univ.), Masanori Nobe (MHPS), Masaharu Tanaka (MHI), Yuichiro Shibata, Hidenori Maruta, Fujio Kurokawa (Nagasaki Univ.)
pp. 33 - 38

RECONF2015-39
ZYNQ CLUSTER FOR CFD PARAMETRIC SURVEY
Naru Sugimoto, Hideharu Amano (Keio Univ.)
pp. 39 - 44

RECONF2015-40
Overview of the Reconfigurable Virtual Accelerator ReVA
Hironori Nakajo, Yuki Oigo (TUAT), Shozo Takeoka (AXE), Masashi Takemoto (BeatCraft), Takefumi Miyoshi (Wasalabo)
pp. 45 - 50

RECONF2015-41
[Invited Talk] Measurements and Optimal Controls of Plant Responses based on a SPA (Speaking Plant Approach)
Tetsuo Morimoto (Ehime Univ.)
p. 51

RECONF2015-42
Proposal of small reconfigurable device SePLD using selector
Keisuke Yamamoto, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Takashi Ishiguro (Taiyo Yuden)
pp. 53 - 58

RECONF2015-43
Recovery method of radiation-damaged optically reconfigurable gate arrays
Tomoya Akabe, Minoru Watanabe (Shizuoka Univ.)
pp. 59 - 62

RECONF2015-44
A Design Method Using Discrete Particle Swarm Optimization for a Deep Neural Network Based on Nested RNS
Tatsuya Ogawa, Hiroki Nakahara (Ehime Univ.), Tsutomu Sasao (Meiji Univ.)
pp. 63 - 68

RECONF2015-45
An Implementation of AND-EXOR Programmable Logic Arrays Using FPGA primitives
Takahiro Shinohara, Hiroki Nakahara (Ehime Univ.), Tsutomu Sasao (Meiji Univ.)
pp. 69 - 73

RECONF2015-46
An Approach with DSL for Building up FPGA Primitives
Takefumi Miyoshi (WasaLabo/e-tress), Satoshi Funada (e-trees)
pp. 75 - 80

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan