IEICE Technical Report

Online edition: ISSN 2432-6380

Reconfigurable Systems

Workshop Date : 2020-09-10 - 2020-09-11 / Issue Date : 2020-09-03

RECONF2020-19
With GPU-FPGA Heterogeneous computing, Highly Effective Communication for Distributed Deep Learning
Kenji Tanaka, Yuki Arikawa, Tsuyoshi Ito, Kazutaka Morita, Naru Nemoto, Fumiaki Miura, Kazuhiko Terada, Junji Teramoto, Takashi Sakamoto (NTT)
pp. 1 - 6

RECONF2020-20
(See Japanese page.)
pp. 7 - 12

RECONF2020-21
Development of Multi-tenant Resource Management for Multi-FPGA Cloud Systems
Miho Yamakura (Keio Univ./AIST), Ryousei Takano, Akram Ben Ahmed (AIST), Hideharu Amano (Keio Univ.)
pp. 13 - 18

RECONF2020-22
(See Japanese page.)
pp. 19 - 24

RECONF2020-23
An implementation of an object detection algorhythm on Vitis AI and Winning a prize in the 2nd AI Edge
Katsunoshin Matsui, Hiromu Miyazaki, Kazuki Nakano, Kenji Kise (Tokyo Tech)
pp. 25 - 29

RECONF2020-24
(See Japanese page.)
pp. 30 - 35

RECONF2020-25
(See Japanese page.)
pp. 36 - 41

RECONF2020-26
(See Japanese page.)
pp. 42 - 47

RECONF2020-27
An FPGA-Based Low-Latency Accelerator for Randomly Wired Convolutional Neural Networks
Ryosuke Kuramochi, Hiroki Nakahara (Tokyo Tech)
pp. 48 - 53

RECONF2020-28
Inductive Invariant Generation Based on Binary Decision Diagram and its Application to Logic Synthesis
Liu ZiHao, Miyasaka Yukio, Fujita Masahiro (UT)
pp. 54 - 59

RECONF2020-29
TAI Compiler: Deep Learning Inference Optimizer for an FPGA
Hiroki Nakahara (TAI)
pp. 60 - 65

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan