IEICE Technical Report

Online edition: ISSN 2432-6380

Computer Systems

Workshop Date : 2021-07-20 - 2021-07-21 / Issue Date : 2021-07-13

CPSY2021-1
Content addressable memory using multi-level cell phase-change memory
Tomohiro Takahashi, Kazuteru Namba (Chiba Univ.)
pp. 1 - 6

CPSY2021-2
Prototype Implementation of Non-Volatile Memory Support for RISC-V Keystone Enclave
Lena Yu, Yu Omori, Keiji Kimura (Waseda Univ.)
pp. 7 - 12

CPSY2021-3
(See Japanese page.)
pp. 13 - 18

CPSY2021-4
A study of inter-node communication on a tightly coupled FPGA cluster
Ryohei Niwase, Hikaru Harasawa, Fan Ruochong, Yoshiki Yamaguchi, Taisuke Boku (Univ. of Tsukuba)
pp. 19 - 24

CPSY2021-5
(See Japanese page.)
pp. 25 - 30

CPSY2021-6
A DPDK-Based Acceleration Method for Experience Sampling of Distributed Reinforcement Learning
Masaki Furukawa, Hiroki Matsutani (Keio Univ.)
pp. 31 - 36

CPSY2021-7
Lossy Error Correction Coding for Vector-Matrix Multiplication
Leo Otani, Haruhiko Kaneko (Tokyo Tech)
pp. 37 - 42

CPSY2021-8
(See Japanese page.)
pp. 43 - 48

CPSY2021-9
(See Japanese page.)
pp. 49 - 52

CPSY2021-10
A Domain Adaptation Method using Light-Weight Neural ODE for Low-Cost FPGAs
Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani (Keio Univ.)
pp. 53 - 58

CPSY2021-11
Development of Spiking Neural Network Using Mem Capacitor
Atsushi Sawada, Reon Oshio, Takeshi Nomura, Renyuan Zhang, Mutsumi Kimura, Yasuhiko Nakashima (NAIST)
pp. 59 - 63

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan