Online edition: ISSN 2432-6380
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RECONF2024-42
(See Japanese page.)
pp. 1 - 6
RECONF2024-43
Improving Drone SLAM Efficiency through Approximate Computing in Levenberg-Marquardt Based Bundle Adjustment
Li Mingkun, Soramichi Akiyama (Ritsumeikan Univ.)
pp. 7 - 12
RECONF2024-44
(See Japanese page.)
pp. 13 - 17
RECONF2024-45
Performance Evaluation of eFPGA Using a New Programmable Logic Element: PAE Cell
Ryo Iwasaki, Tatsuya Sasaki, Kenshu Seto, Masahiro Iida (Kumamoto Univ.)
pp. 18 - 23
RECONF2024-46
CGRA architecture exploration towards post-moore HPC and AI accelerators
Boma Adhi, Emanuele del Sozzo, Kentaro Sano (R-CCS)
pp. 24 - 29
RECONF2024-47
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p. 30
RECONF2024-48
Long distance communication using a radiation-hardened optically reconfigurable gate array
Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)
pp. 31 - 34
RECONF2024-49
A Table Look-Up based Quantum Simulation Accelerator on an FPGA
Hasegawa Haruhiko (Tokyo Tech), Nakahara Hiroki (THK)
pp. 35 - 40
RECONF2024-50
Chisel Implementation and Evaluation of Adaptive Bandwidth Compression Hardware Platform
Kaito Kitazume (Univ. of Tsukuba), Tomohiro Ueno (RIKEN), Kazutomo Yoshii (ANL), Masato Kiyama (Kumamoto Univ.), Norihisa Fujita, Ryohei Kobayashi (Univ. of Tsukuba), Kentaro Sano (RIKEN), Taisuke Boku (Univ. of Tsukuba)
pp. 41 - 46
RECONF2024-51
Prototype Development for High-Efficiency Chip-to-Chip Communication Using Ultra-Parallel Buses in 3D-Stacked LSI
Yuto Shiota, Kuboki Takeshi, Aoyagi Masahiro, Ohkawa Takeshi (Kumamoto uni)
pp. 47 - 52
RECONF2024-52
Development of a Prototype System for Measuring Temperature Distribution and Temporal Changes in 3D-LSI
Masaki Nakamura, Takeshi Kuboki, Masahiro Aoyagi, Takeshi Ohkawa (Kumamoto Univ.)
pp. 53 - 58
RECONF2024-53
(See Japanese page.)
p. 59
RECONF2024-54
Shell-Role style FPGA chip SLMLET-2 for IoT applications
Hideharu Amano, Takuya Kojima (U. Tokyo), Morihiro Kuga (Kumamoto Univ.), Hayate Okuhara (NUS), Masahiro Iida (Kumamoto Univ.)
pp. 60 - 65
RECONF2024-55
Development of improved eFPGA-IP for MEC devices
Zhan Yan, Koudai Takeno, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.)
pp. 66 - 71
RECONF2024-56
Consideration of floorplan of DSP block in FPGA-IP for MEC device
Kodai Takeno, Zhan Yan, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.)
pp. 72 - 78
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.