IEICE Technical Report

Online edition: ISSN 2432-6380

Reconfigurable Systems

Workshop Date : 2025-06-09 - 2025-06-11 / Issue Date : 2025-06-02

RECONF2025-1
A Storage System with Autonomous Control of Cache Policy and Size Based on IO Locality
Kazuichi Oe, Kento Aida (NII)
pp. 1 - 12

RECONF2025-2
Towards High-Performance NVMe SSD Management with FPGA Architecture
Shu Kikkawa, Yoshiki Yamaguchi (University of Tsukuba)
pp. 13 - 18

RECONF2025-3
Evaluation of a Deterministic Concurrency Control Protocol using GPU
Koki Matsushima, Hideyuki Kawashima (Keio Univ.)
pp. 19 - 23

RECONF2025-4
Performance Evaluation of Cryptographic Operations in a WebAssembly Execution Environment for TEE
Koichi Hashimoto, Shogo Takata, Haruki Kawai, Sota Nakumura, Akira Yoshida (TUAT), Yutaka Ishikawa (ROIS), Hironori Nakajo (TUAT)
pp. 24 - 29

RECONF2025-5
Hardware-Oriented Neural Network Model Exploration for Variable-Parallelism Reconfigurable Architecture
Yu Inoue, Atsushi Hori, Takao Marukame, Tetsuya Asai (Hokkaido Univ.), Alexandre Schmid (EPFL), Kota Ando (Hokkaido Univ.)
pp. 30 - 35

RECONF2025-6
Efficient memory access in variable-parallelism architectures for DNN inference
Atsushi Hori, Yu Inoue, Fumiya Arai, Takao Marukame, Tetsuya Asai, Kota Ando (Hokkaido Univ.)
pp. 36 - 41

RECONF2025-7
[Special Invited Talk] Computing using Light: Photonic Devices for Large-Scale Optical Processing -- Can Optical Circuits Enable Scalable Computation? --
Toshikazu Hashimoto (NTT)
pp. 42 - 45

RECONF2025-8
[Special Invited Talk] Towards Emerging Device Computing: Pros and Cons -- Discussion for Next-Generation Computer Architecture Research --
Koji Inoue (Kyushu University)
p. 46

RECONF2025-9
[Invited Talk] Material reservoir computing based on carbon nanotube/functional molecule random network
Yuki Usami, Shuho Murazoe, Yuto Koga, Deep Banerjee, Hirofumi Tanaka (Kyutech)
p. 47

RECONF2025-10
Unique resistive switching characteristics using graphene/sumanene/graphene stacked structures
Ryoichi Kawai, Yoshiharu Kirihara, Reika Fujie, Kana Tabata, Ryosuke Katsumata, Kaito Kimijima, Ryousuke Ishikawa, Hiroshi Nohira, Yuichiro Mitani (TCU)
pp. 48 - 52

RECONF2025-11
A WebSocket interface design for bare-metal OS based FPGA
Kensuke Tozaki, Yusuke Hara, Shinji Fukuma (Univ. Fukui)
pp. 53 - 58

RECONF2025-12
CFU Proving Ground: a framework for efficiently utilizing custom instructions in RISC-V soft processors
Aoba Fujino, Kenji Kise (Science Tokyo)
pp. 59 - 64

RECONF2025-13
X-filling Method for Control signals of Controllers to Reduce the Number of Estimated Patterns
Haruta Tokuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.)
pp. 65 - 70

RECONF2025-14
(See Japanese page.)
pp. 71 - 76

RECONF2025-15
A Test Pattern Replacement Method to Achieve Both Complete Fault Efficiency and Complete Diagnostic Resolution for Transition Faults
Tatsuya Aono, Toshinori Hosokawa (Nihon Univ.), Masayoshi Moshinura (Kyoto Sangyo Univ.), Koji Yamazaki (Meiji Univ.), Masayuki Arai (Nihon Univ.)
pp. 77 - 82

RECONF2025-16
Accelerating Elliptic Curve Point Additions on Versal AI Engine
Ayumi Ohno (Utokyo), Shinya Takamaeda (Utokyo/RIKEN)
pp. 83 - 88

RECONF2025-17
Evaluation of YOLOX-Nano Quantization Accuracy Leveraging Edge AI acceleratos
Hiroto Iwanaga, Chikako Nakanishi (OIT)
pp. 89 - 93

RECONF2025-18
Evaluation of MNIST with AI Accelerators in Edge AI
Takanori Kamakura, Chikako Nakanishi (OIT)
pp. 94 - 97

RECONF2025-19
(See Japanese page.)
pp. 98 - 103

RECONF2025-20
Investigation and Evaluation of Static Allocation Methods for Backup Control Processes in Highly Available Systems
Shintaro Kudo, Hiroaki Akutsu (Hitachi)
pp. 104 - 109

RECONF2025-21
RUNLTS: A Branch Prediction Algorithm for Out-of-Order CPUs and Its Evaluation Using the Championship Branch Prediction 2025 Framework
Masanari Mizuno, Toru Koizumi, Toshiki Maekawa (NITech), Maru Kuroki (UTokyo), Tomoaki Tsumura (NITech), Ryota Shioya (UTokyo)
pp. 110 - 115

RECONF2025-22
Efficient Implementation of SHA256 Hardware with XLS Open-Source High-Level Synthesis
Yoshiki Ozaki (UT), Shinya Takamaeda-Yamazaki (UTokyo/RIKEN)
pp. 116 - 121

RECONF2025-23
A study of Multi-Core CRYSTALS-Kyber Accelerator Based on a RISC-V Processor
Kien Tran-Hoang, Hironori Nakajo (TUAT)
pp. 122 - 127

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan