IEICE Technical Report

Online edition: ISSN 2432-6380

Reconfigurable Systems

Workshop Date : 2026-09-14 - 2026-09-15 / Issue Date : 2026-09-07

RECONF2026-37
[Invited Talk] A Development History of Yamaha Voice Communication Systems -- Satisfying Audio Quality, Usability and Cost in the YVC-1000 --
Ryo Tanaka (Yamaha)
pp. 1 - 6

RECONF2026-38
FPGA Implementation of a Parallel Distributed Processing Architecture for Real-Time Physical Simulation of Piano Body and Strings
Tomoaki Ando, Masatsugu Okazaki (Yamaha)
pp. 7 - 12

RECONF2026-39

Miao Jiaqi, Ohkawa Takeshi (Kumamoto Univ.)
pp. 13 - 18

RECONF2026-40
High-Level Synthesis Design and Performance Evaluation of Data-Consistency Relaxation for Pipelined Informed RRT* on FPGAs
Koh Tomita (Univ. of Tsukuba), Tomonori Izumi (Ritsumeikan Univ.), Yoshiki Yamaguchi (Univ. of Tsukuba/Kumamoto Univ.)
pp. 19 - 24

RECONF2026-41
(See Japanese page.)
pp. 25 - 29

RECONF2026-42
(See Japanese page.)
pp. 30 - 31

RECONF2026-43

Akinobu Tomori, Masaya Ando, Yasunori Osana (Kumamoto Univ.)
pp. 32 - 36

RECONF2026-44
Time-Division Multiplexing of Rate-Imbalanced Lossless Compressed Data Channels on FPGAs
Takato Abe (Univ. of Tsukuba), Tomohiro Ueno (RIKEN), Norihisa Fujita (Univ. of Tsukuba)
pp. 37 - 42

RECONF2026-45
(See Japanese page.)
pp. 43 - 45

RECONF2026-46
A Case for Extending Int2FP accelerator IP for RISC-V based SoC into FPGA-Based Cycle-Accurate Simulation via FireSim
Nuttapat Tamprasert, Kou Ishikura, Yukinori Sato (Toyohashi Univ. of Tech.)
pp. 46 - 51

RECONF2026-47
A Proposal and Evaluation of an Instruction-Less Computing Method Using an eFPGA
Ryo Iwasaki, Tenpei Oda, Souta Kohata, Masaya Ueda, Kai Ito, Masato Kiyama, Masahiro Iida (Kumamoto Univ.)
pp. 52 - 57

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan