| Paper Abstract and Keywords |
| Presentation |
2004-06-17 15:15
A New Digital Architecture of Inverse Function Delayed Neuron with the Stochastic Logic
Hongge Li, Yoshihiro Hayakawa, Shigeo Sato, Koji Nakajima (Tohoku Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
In this paper, we present a new digital architecture for neuron hardware that can be implemented using the field programmable gate array (FPGA). The proposed neuron provides a new neuron model of Inverse function Delayed. In order to implement the ID model, we employ a new architecture of inverse function with the stochastic logic. Since the property of stochastic logic, the scale of circuit is smaller than the conventional digital circuit. On the other hand, the stochastic logic requires the certain accumulation time for averaging. The simulation experimental results show that the inverse function variance is relationship with the accumulation time, and this digital system can perform the associative memory. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
stochastic logic / inverse function / ID model / FPGA / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 104, no. 112, NLP2004-19, pp. 29-34, June 2004. |
| Paper # |
NLP2004-19 |
| Date of Issue |
2004-06-10 (NLP) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
NLP |
| Conference Date |
2004-06-17 - 2004-06-17 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Tottori Kenritsu Shogai Gakushu Center |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
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| Paper Information |
| Registration To |
NLP |
| Conference Code |
2004-06-NLP |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
A New Digital Architecture of Inverse Function Delayed Neuron with the Stochastic Logic |
| Sub Title (in English) |
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| Keyword(1) |
stochastic logic |
| Keyword(2) |
inverse function |
| Keyword(3) |
ID model |
| Keyword(4) |
FPGA |
| Keyword(5) |
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| 1st Author's Name |
Hongge Li |
| 1st Author's Affiliation |
Tohoku Univ. (Tohoku Univ.) |
| 2nd Author's Name |
Yoshihiro Hayakawa |
| 2nd Author's Affiliation |
Tohoku Univ. (Tohoku Univ.) |
| 3rd Author's Name |
Shigeo Sato |
| 3rd Author's Affiliation |
Tohoku Univ. (Tohoku Univ.) |
| 4th Author's Name |
Koji Nakajima |
| 4th Author's Affiliation |
Tohoku Univ. (Tohoku Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2004-06-17 15:15:00 |
| Presentation Time |
25 minutes |
| Registration for |
NLP |
| Paper # |
NLP2004-19 |
| Volume (vol) |
vol.104 |
| Number (no) |
no.112 |
| Page |
pp.29-34 |
| #Pages |
6 |
| Date of Issue |
2004-06-10 (NLP) |