Paper Abstract and Keywords |
Presentation |
2004-12-16 10:30
A Dynamic SDRAM-Mode Control Scheme for Low-Power Systems Seiji Miura, Kazushige Ayukawa (Hitachi,Ltd) Link to ES Tech. Rep. Archives: ICD2004-184 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A dynamic SDRAM-mode-control scheme for low-power systems was developed and tested. The scheme is based on two dynamic changes of SDRAM modes: from active standby to standby and from standby to active standby. It reduces both the operating current and the latency of an SDRAM. An analysis using benchmark programs shows that the developed scheme reduces the SDRAM operating current by 40% and latency by 38% compared to those in standby mode. An SDRAM controller based on this scheme and 0.18-um CMOS technology was developed. The area of the controller is 0.28mm2, and its operating current is 2.5mA at 1.8V and 100 MHz. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SDRAM controller / standby mode / active-standby mode / latency / low power / / / |
Reference Info. |
IEICE Tech. Rep., vol. 104, no. 521, ICD2004-184, pp. 7-11, Dec. 2004. |
Paper # |
ICD2004-184 |
Date of Issue |
2004-12-09 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
Link to ES Tech. Rep. Archives: ICD2004-184 |
Conference Information |
Committee |
ICD |
Conference Date |
2004-12-16 - 2004-12-17 |
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Registration To |
ICD |
Conference Code |
2004-12-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Dynamic SDRAM-Mode Control Scheme for Low-Power Systems |
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SDRAM controller |
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standby mode |
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active-standby mode |
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latency |
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low power |
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1st Author's Name |
Seiji Miura |
1st Author's Affiliation |
Hitachi,Ltd (Hitachi,Ltd) |
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Kazushige Ayukawa |
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Hitachi,Ltd (Hitachi,Ltd) |
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Speaker |
Author-1 |
Date Time |
2004-12-16 10:30:00 |
Presentation Time |
30 minutes |
Registration for |
ICD |
Paper # |
ICD2004-184 |
Volume (vol) |
vol.104 |
Number (no) |
no.521 |
Page |
pp.7-11 |
#Pages |
5 |
Date of Issue |
2004-12-09 (ICD) |
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