| Paper Abstract and Keywords |
| Presentation |
2005-09-15 15:00
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
Zhangcai Huang (Waseda Univ.), Atsushi Kurukawa (STAC), Yasuaki Inoue (Waseda Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
In deep submicron designs, predicting
gate slews and delays for interconnect loads is vitally
important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay
of interconnect loads. However, less work has been
done to develop a Ceff algorithm which can accurately
predict gate slew. In this paper, we propose a novel
method for calculating the Ceff of interconnect load
for gate slew. The simulation results demonstrate a
significant improvement in accuracy. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Static Timing Analysis / gate slew / interconnect load / effective capacitance / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 105, no. 276, NLP2005-44, pp. 31-36, Sept. 2005. |
| Paper # |
NLP2005-44 |
| Date of Issue |
2005-09-08 (CAS, NLP) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
CAS NLP |
| Conference Date |
2005-09-15 - 2005-09-16 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Nagaoka Univ. of Technology |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
general |
| Paper Information |
| Registration To |
NLP |
| Conference Code |
2005-09-CAS-NLP |
| Language |
English |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew |
| Sub Title (in English) |
|
| Keyword(1) |
Static Timing Analysis |
| Keyword(2) |
gate slew |
| Keyword(3) |
interconnect load |
| Keyword(4) |
effective capacitance |
| Keyword(5) |
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| Keyword(6) |
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| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Zhangcai Huang |
| 1st Author's Affiliation |
Waseda University (Waseda Univ.) |
| 2nd Author's Name |
Atsushi Kurukawa |
| 2nd Author's Affiliation |
The Semiconductor Technology Academic Research Center (STAC) |
| 3rd Author's Name |
Yasuaki Inoue |
| 3rd Author's Affiliation |
Waseda University (Waseda Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2005-09-15 15:00:00 |
| Presentation Time |
25 minutes |
| Registration for |
NLP |
| Paper # |
CAS2005-31, NLP2005-44 |
| Volume (vol) |
vol.105 |
| Number (no) |
no.274(CAS), no.276(NLP) |
| Page |
pp.31-36 |
| #Pages |
6 |
| Date of Issue |
2005-09-08 (CAS, NLP) |
|