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| Presentation | 2006-04-13 10:45 [Special Invited Talk] Sub-1V DRAM Design Takayuki Kawahara (Hitachi Central Research Lab.) Link to ES Tech. Rep. Archives:  ICD2006-4 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Issues for sub-1V DRAM operation and its solutions are described. Since the low voltage operation of DRAM is difficult, the usefulness of sub-1V is firstly discussed from the viewpoint of power dissipation, reliability and system configuration. But the word-line voltage needs to generate as a boosted one. Signal charge is decreasing due to low-voltage operation; low-noise array, divided bit-line, and ECC are needed. Accordingly, design of sense amplifier becomes crucial in the inevitable increasing of threshold voltage mismatch of pair transistors and by causing small operating margin. The developments of off-set cancellation, pre-amplification, and overdriven sense amplifier are desired. As for increasing leakage current, since DRAM uses many iterative circuits and predictable logic, the leakage reduction technique combined with this features is necessary. And preceding discussion of sub-1V circuits in SRAM and logic suggests the serious problem of variation of threshold voltage of transistor. Their solution of thin BOX FD-SOI will be a good candidate for DRAM also. In addition, a high voltage word line driving is necessary even in sub-1V operation according to DRAM’s principle, charge pumps with high boost ratio with reference voltage generator under sub-1V are the subject. Furthermore, the reduction of speed variation of peripheral circuits in a chip due to the transistor variation will also need to be handled. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | DRAM / sub-1V / threshold voltage mismatch / leakage current / charge pump / FD-SOI / sense amplifier / SRAM | |
| Reference Info. | IEICE Tech. Rep., vol. 106, no. 2, ICD2006-4, pp. 19-24, April 2006. | |
| Paper # | ICD2006-4 | |
| Date of Issue | 2006-04-06 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2006-4 |
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| Conference Information | |
| Committee | ICD |
| Conference Date | 2006-04-13 - 2006-04-14 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Oita University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2006-04-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Sub-1V DRAM Design |
| Sub Title (in English) | |
| Keyword(1) | DRAM |
| Keyword(2) | sub-1V |
| Keyword(3) | threshold voltage mismatch |
| Keyword(4) | leakage current |
| Keyword(5) | charge pump |
| Keyword(6) | FD-SOI |
| Keyword(7) | sense amplifier |
| Keyword(8) | SRAM |
| 1st Author's Name | Takayuki Kawahara |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi Ltd. (Hitachi Central Research Lab.) |
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| Speaker | Author-1 |
| Date Time | 2006-04-13 10:45:00 |
| Presentation Time | 50 minutes |
| Registration for | ICD |
| Paper # | ICD2006-4 |
| Volume (vol) | vol.106 |
| Number (no) | no.2 |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2006-04-06 (ICD) |
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