| Paper Abstract and Keywords |
| Presentation |
2006-05-12 11:15
Power-Conscious Microprocessor-Based Testing of System-on-Chip
Fawnizu Azmadi Hussin, Tomokazu Yoneda (NAIST), Alex Orailoglu (Univ. of California), Hideo Fujiwara (NAIST) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the generation of a complete test schedule that efficiently utilizes the functional bus under a power constraint is described. The test schedule is composed of a set of test vector delivery sequences in small chunks, denoted as packets. The utilization of small packet sizes minimizes required buffer sizes while optimizing the functional bus utilization. The experimental results show that the methodology is highly effective compared to previous approaches that do not use the functional bus. The strong results of the proposed approach are particularly highlighted when small bus widths are considered, an important consideration in current SOC designs where increasingly larger bus widths pose routing and reliability challenges. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Functional bus / Microprocessor-based / Power-Constrained / Test Packet / Test Scheduling / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 106, no. 32, VLD2006-10, pp. 25-30, May 2006. |
| Paper # |
VLD2006-10 |
| Date of Issue |
2006-05-05 (VLD) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
VLD IPSJ-SLDM |
| Conference Date |
2006-05-11 - 2006-05-12 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Ehime University |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
|
| Paper Information |
| Registration To |
VLD |
| Conference Code |
2006-05-VLD-IPSJ-SLDM |
| Language |
English |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Power-Conscious Microprocessor-Based Testing of System-on-Chip |
| Sub Title (in English) |
|
| Keyword(1) |
Functional bus |
| Keyword(2) |
Microprocessor-based |
| Keyword(3) |
Power-Constrained |
| Keyword(4) |
Test Packet |
| Keyword(5) |
Test Scheduling |
| Keyword(6) |
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| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Fawnizu Azmadi Hussin |
| 1st Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
| 2nd Author's Name |
Tomokazu Yoneda |
| 2nd Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
| 3rd Author's Name |
Alex Orailoglu |
| 3rd Author's Affiliation |
University of California (Univ. of California) |
| 4th Author's Name |
Hideo Fujiwara |
| 4th Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
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| Speaker |
Author-1 |
| Date Time |
2006-05-12 11:15:00 |
| Presentation Time |
30 minutes |
| Registration for |
VLD |
| Paper # |
VLD2006-10 |
| Volume (vol) |
vol.106 |
| Number (no) |
no.32 |
| Page |
pp.25-30 |
| #Pages |
6 |
| Date of Issue |
2006-05-05 (VLD) |