Paper Abstract and Keywords |
Presentation |
2006-05-25 13:00
A 40GOPS 250mW Massively Parallel Processor Based on Matrix Architecture
-- A Very High Performance Processor IP for Mobile System-on-Chips -- Kiyoshi Nakata, Masami Nakajima, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten (Renesas) Link to ES Tech. Rep. Archives: ICD2006-25 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We have developed a massively parallel processor based on Matrix architecture. This architecture achieved 40GOPS of 16-bit additions at 200MHz clock frequency and 250mW power dissipation. Data registers based on SRAM and 2,048 processing elements connected by flexible switching network are integrated in 3.1mm2 by 90nm low-power CMOS. This Matrix architecture with effective energy efficiency supports the 2,048-way parallel operation and the programmable functions suitable for multimedia SoC. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Matrix / Massively Parallel processing / Low power / Multimedia / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 106, no. 71, ICD2006-25, pp. 19-23, May 2006. |
Paper # |
ICD2006-25 |
Date of Issue |
2006-05-18 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
Link to ES Tech. Rep. Archives: ICD2006-25 |
Conference Information |
Committee |
ICD |
Conference Date |
2006-05-25 - 2006-05-26 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kobe University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
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Paper Information |
Registration To |
ICD |
Conference Code |
2006-05-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A 40GOPS 250mW Massively Parallel Processor Based on Matrix Architecture |
Sub Title (in English) |
A Very High Performance Processor IP for Mobile System-on-Chips |
Keyword(1) |
Matrix |
Keyword(2) |
Massively Parallel processing |
Keyword(3) |
Low power |
Keyword(4) |
Multimedia |
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1st Author's Name |
Kiyoshi Nakata |
1st Author's Affiliation |
Renesas Technology Corp. (Renesas) |
2nd Author's Name |
Masami Nakajima |
2nd Author's Affiliation |
Renesas Technology Corp. (Renesas) |
3rd Author's Name |
Hideyuki Noda |
3rd Author's Affiliation |
Renesas Technology Corp. (Renesas) |
4th Author's Name |
Tetsushi Tanizaki |
4th Author's Affiliation |
Renesas Technology Corp. (Renesas) |
5th Author's Name |
Takayuki Gyohten |
5th Author's Affiliation |
Renesas Technology Corp. (Renesas) |
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Speaker |
Author-1 |
Date Time |
2006-05-25 13:00:00 |
Presentation Time |
30 minutes |
Registration for |
ICD |
Paper # |
ICD2006-25 |
Volume (vol) |
vol.106 |
Number (no) |
no.71 |
Page |
pp.19-23 |
#Pages |
5 |
Date of Issue |
2006-05-18 (ICD) |