| Paper Abstract and Keywords |
| Presentation |
2006-06-22 16:15
Re-placement Method for Circuit Modification
Kunihiko Yanagibashi, Yasuhiro Takashima (Univ. of Kitakyushu) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
This paper proposes a re-placement method for circuit modification．The re-placement is required to realize a placement with small area in a short time，while the similarity to the previous placement is kept．For the objective，the proposed algorithm employs to minimize the sum of differences of the length of each wire from the one in the previous placement．We propose a non full-reverse-order constraint，which is obtained by relaxing the topological relation in the previous placement． The constraint leads the resultant placement similar to the previous one in terms of the topology．The optimization method for re-placement is simulated annealing．Since the modification of re-placement is local， we limit the modification range around the added module．As a result，an efficient and high-speed re-placement is achieved．Experimental results demonstrate that the proposed algorithm is effective and efficient． |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Non full-reverse-order constraint / Circuit Modification / Re-placement / Sequence-Pair / Simulated Annealing / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 106, no. 113, VLD2006-20, pp. 35-40, June 2006. |
| Paper # |
VLD2006-20 |
| Date of Issue |
2006-06-15 (CAS, VLD, SIP) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
SIP CAS VLD |
| Conference Date |
2006-06-22 - 2006-06-23 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Kitami Institute of Technology |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Signal Processing, LSI, etc |
| Paper Information |
| Registration To |
VLD |
| Conference Code |
2006-06-SIP-CAS-VLD |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Re-placement Method for Circuit Modification |
| Sub Title (in English) |
|
| Keyword(1) |
Non full-reverse-order constraint |
| Keyword(2) |
Circuit Modification |
| Keyword(3) |
Re-placement |
| Keyword(4) |
Sequence-Pair |
| Keyword(5) |
Simulated Annealing |
| Keyword(6) |
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| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Kunihiko Yanagibashi |
| 1st Author's Affiliation |
the University of Kitakyushu (Univ. of Kitakyushu) |
| 2nd Author's Name |
Yasuhiro Takashima |
| 2nd Author's Affiliation |
the University of Kitakyushu (Univ. of Kitakyushu) |
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| Speaker |
Author-1 |
| Date Time |
2006-06-22 16:15:00 |
| Presentation Time |
25 minutes |
| Registration for |
VLD |
| Paper # |
CAS2006-7, VLD2006-20, SIP2006-30 |
| Volume (vol) |
vol.106 |
| Number (no) |
no.111(CAS), no.113(VLD), no.115(SIP) |
| Page |
pp.35-40 |
| #Pages |
6 |
| Date of Issue |
2006-06-15 (CAS, VLD, SIP) |