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Paper Abstract and Keywords
Presentation 2006-08-18 12:05
A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC
Susumu Imaoka (Renesas Design), Koji Nii (Renesas Technology), Yasuhiro Masuda (Renesas Design), Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Motoshige Igarashi, Kazuo Tomita, Nobuo Tsuboi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology)
Abstract (in Japanese) (See Japanese page) 
(in English) We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71um2 8T-DP-cell, which cell size is 1.44x larger than 6T-single-port (SP)-cell.
Keyword (in Japanese) (See Japanese page) 
(in English) SRAM / dual-port / 8T-cell / SNM / 65nm / hp90 / SoC / high-density  
Reference Info. IEICE Tech. Rep., vol. 106, no. 206, SDM2006-148, pp. 133-136, Aug. 2006.
Paper # SDM2006-148 
Date of Issue 2006-08-10 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685
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Conference Information
Committee ICD SDM  
Conference Date 2006-08-17 - 2006-08-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Hokkaido University 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SDM 
Conference Code 2006-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC 
Sub Title (in English)  
Keyword(1) SRAM  
Keyword(2) dual-port  
Keyword(3) 8T-cell  
Keyword(4) SNM  
Keyword(5) 65nm  
Keyword(6) hp90  
Keyword(7) SoC  
Keyword(8) high-density  
1st Author's Name Susumu Imaoka  
1st Author's Affiliation Renesas Design Corporation (Renesas Design)
2nd Author's Name Koji Nii  
2nd Author's Affiliation Renesas Technology Corporation (Renesas Technology)
3rd Author's Name Yasuhiro Masuda  
3rd Author's Affiliation Renesas Design Corporation (Renesas Design)
4th Author's Name Makoto Yabuuchi  
4th Author's Affiliation Renesas Technology Corporation (Renesas Technology)
5th Author's Name Yasumasa Tsukamoto  
5th Author's Affiliation Renesas Technology Corporation (Renesas Technology)
6th Author's Name Shigeki Ohbayashi  
6th Author's Affiliation Renesas Technology Corporation (Renesas Technology)
7th Author's Name Motoshige Igarashi  
7th Author's Affiliation Renesas Technology Corporation (Renesas Technology)
8th Author's Name Kazuo Tomita  
8th Author's Affiliation Renesas Technology Corporation (Renesas Technology)
9th Author's Name Nobuo Tsuboi  
9th Author's Affiliation Renesas Technology Corporation (Renesas Technology)
10th Author's Name Hiroshi Makino  
10th Author's Affiliation Renesas Technology Corporation (Renesas Technology)
11th Author's Name Koichiro Ishibashi  
11th Author's Affiliation Renesas Technology Corporation (Renesas Technology)
12th Author's Name Hirofumi Shinohara  
12th Author's Affiliation Renesas Technology Corporation (Renesas Technology)
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Speaker Author-1 
Date Time 2006-08-18 12:05:00 
Presentation Time 25 minutes 
Registration for SDM 
Paper # SDM2006-148, ICD2006-102 
Volume (vol) vol.106 
Number (no) no.206(SDM), no.207(ICD) 
Page pp.133-136 
#Pages 4 
Date of Issue 2006-08-10 (SDM, ICD) 

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