Paper Abstract and Keywords |
Presentation |
2006-08-18 12:05
A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC Susumu Imaoka (Renesas Design), Koji Nii (Renesas Technology), Yasuhiro Masuda (Renesas Design), Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Motoshige Igarashi, Kazuo Tomita, Nobuo Tsuboi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) Link to ES Tech. Rep. Archives: SDM2006-148 ICD2006-102 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71um2 8T-DP-cell, which cell size is 1.44x larger than 6T-single-port (SP)-cell. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SRAM / dual-port / 8T-cell / SNM / 65nm / hp90 / SoC / high-density |
Reference Info. |
IEICE Tech. Rep., vol. 106, no. 206, SDM2006-148, pp. 133-136, Aug. 2006. |
Paper # |
SDM2006-148 |
Date of Issue |
2006-08-10 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
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Link to ES Tech. Rep. Archives: SDM2006-148 ICD2006-102 |
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