| Paper Abstract and Keywords |
| Presentation |
2006-09-06 15:10
Boundary Processing of Thin Conductor Plates and Conductor Corners in the FDTD Method Standpoint of Lattice Spacing and Arrangement
Satoru Ikeuti (Panasonic ED Nitto), Yukio Iida, Hiroaki Miula (Kansai Univ.), Toshiaki Nakamura (Panasonic ED Nitto) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
In the FDTD method, when the structure with the conductor edges and corners is analyzed, the computation errors by the field singularity are important subjects. In this paper, the modeling of thin strip conductor and conductor with corner are studied from the standpoint of grid arrangement. The strip-line resonator (SLR) and the cavity with capacitive iris are chosen as analytical models, and the variations in the resonant frequency for the grid arrangement types and FDTD cell size are examined. As a result, when offset grid arrangement is applied to thin conductor plate and the conductor corner, the possibility that the error margin can be considerably reduced is pointed out compared with usual boundary processing. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
FDTD method / computation accuracy / offset lattice arrangement / thin conductor plate / conductor corner / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 106, no. 231, MW2006-100, pp. 139-144, Sept. 2006. |
| Paper # |
MW2006-100 |
| Date of Issue |
2006-08-29 (MW) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
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| Conference Information |
| Committee |
MW |
| Conference Date |
2006-09-05 - 2006-09-07 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
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| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
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| Paper Information |
| Registration To |
MW |
| Conference Code |
2006-09-MW |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Boundary Processing of Thin Conductor Plates and Conductor Corners in the FDTD Method Standpoint of Lattice Spacing and Arrangement |
| Sub Title (in English) |
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| Keyword(1) |
FDTD method |
| Keyword(2) |
computation accuracy |
| Keyword(3) |
offset lattice arrangement |
| Keyword(4) |
thin conductor plate |
| Keyword(5) |
conductor corner |
| Keyword(6) |
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| Keyword(7) |
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| 1st Author's Name |
Satoru Ikeuti |
| 1st Author's Affiliation |
Panasonic Electronic Devices Nitto Co.,Ltd. (Panasonic ED Nitto) |
| 2nd Author's Name |
Yukio Iida |
| 2nd Author's Affiliation |
Kansai University (Kansai Univ.) |
| 3rd Author's Name |
Hiroaki Miula |
| 3rd Author's Affiliation |
Kansai University (Kansai Univ.) |
| 4th Author's Name |
Toshiaki Nakamura |
| 4th Author's Affiliation |
Panasonic Electronic Devices Nitto Co.,Ltd. (Panasonic ED Nitto) |
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| Speaker |
Author-2 |
| Date Time |
2006-09-06 15:10:00 |
| Presentation Time |
25 minutes |
| Registration for |
MW |
| Paper # |
MW2006-100 |
| Volume (vol) |
vol.106 |
| Number (no) |
no.231 |
| Page |
pp.139-144 |
| #Pages |
6 |
| Date of Issue |
2006-08-29 (MW) |