| Paper Abstract and Keywords |
| Presentation |
2006-09-26 10:00
A Processor for Genetic Algorithm using Dynamically Reconfigurable Memory
Akihiko Tsukahara, Akinori Kanasugi (Tokyo Denki Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
This paper proposes a novel processor for genetic algorithm (GA) using dynamically reconfigurable memory. Ingeneral GA, the number of population is always constant. However, the accuracy of the solution is low in the first-half stage. Then, the number of population is doubled at the expense of the accuracy of the solution, and the searching ability is improved in the first-half stage. Moreover, the number of population is reduced by half, and accuracy is improved in the second-half stage. As a result, the searching ability is improved without increasing the memory capacity. The processor was designed by using VHDL and the circuit was simulated. The effectiveness of the proposal processor was confirmed by logic simulations. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Genetic Algorithm / Dynamically Reconstruction / FPGA / / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 106, no. 254, VLD2006-39, pp. 1-6, Sept. 2006. |
| Paper # |
VLD2006-39 |
| Date of Issue |
2006-09-18 (VLD, SDM) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
SDM VLD |
| Conference Date |
2006-09-25 - 2006-09-26 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Process, Device, Circuit Simulation, etc. |
| Paper Information |
| Registration To |
VLD |
| Conference Code |
2006-09-SDM-VLD |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
A Processor for Genetic Algorithm using Dynamically Reconfigurable Memory |
| Sub Title (in English) |
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| Keyword(1) |
Genetic Algorithm |
| Keyword(2) |
Dynamically Reconstruction |
| Keyword(3) |
FPGA |
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| 1st Author's Name |
Akihiko Tsukahara |
| 1st Author's Affiliation |
Tokyo Denki University (Tokyo Denki Univ.) |
| 2nd Author's Name |
Akinori Kanasugi |
| 2nd Author's Affiliation |
Tokyo Denki University (Tokyo Denki Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2006-09-26 10:00:00 |
| Presentation Time |
25 minutes |
| Registration for |
VLD |
| Paper # |
VLD2006-39, SDM2006-160 |
| Volume (vol) |
vol.106 |
| Number (no) |
no.254(VLD), no.256(SDM) |
| Page |
pp.1-6 |
| #Pages |
6 |
| Date of Issue |
2006-09-18 (VLD, SDM) |