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Paper Abstract and Keywords
Presentation 2006-10-05 12:05
Sorter-based Sigma-Delta Domain Multi-level Operators - Part II
Hisato Fujisaka, Takeshi Kamio, Kazuhisa Haeiwa (Hiroshima City Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents a multi-level multipler and multi-level piecewise linear circuits for sigma-delta domain signal processing.The circuits are based on adders built with binary sorting networks.Operations of the proposed circuits are confirmed and their output quality is evaluated.
Keyword (in Japanese) (See Japanese page) 
(in English) sigma-delta modulator / multiplier / piecewise linear circuits / quantization noise / / / /  
Reference Info. IEICE Tech. Rep., vol. 106, no. 275, NLP2006-64, pp. 41-46, Oct. 2006.
Paper # NLP2006-64 
Date of Issue 2006-09-28 (CAS, NLP) 
ISSN Print edition: ISSN 0913-5685
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Conference Information
Committee NLP CAS  
Conference Date 2006-10-04 - 2006-10-05 
Place (in Japanese) (See Japanese page) 
Place (in English)  
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Paper Information
Registration To NLP 
Conference Code 2006-10-NLP-CAS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Sorter-based Sigma-Delta Domain Multi-level Operators - Part II 
Sub Title (in English)  
Keyword(1) sigma-delta modulator  
Keyword(2) multiplier  
Keyword(3) piecewise linear circuits  
Keyword(4) quantization noise  
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1st Author's Name Hisato Fujisaka  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Takeshi Kamio  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Kazuhisa Haeiwa  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Speaker Author-1 
Date Time 2006-10-05 12:05:00 
Presentation Time 25 minutes 
Registration for NLP 
Paper # CAS2006-41, NLP2006-64 
Volume (vol) vol.106 
Number (no) no.273(CAS), no.275(NLP) 
Page pp.41-46 
#Pages
Date of Issue 2006-09-28 (CAS, NLP) 


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