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Presentation 2006-10-26 11:30
Super parallel SIMD processor with CAM based high-speed pattern matching capability
Yutaka Kono, Takeshi Kumaki, Masakatsu Ishizaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yasuto Kuroda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas) Link to ES Tech. Rep. Archives: ICD2006-116
Abstract (in Japanese) (See Japanese page) 
(in English) A super parallel SIMD processor has been developed for handling the increasing amount of
multimedia data efficiently.
It is able to execute the same operation with a large amount of multimedia data at high speed
by changing the conventional word-serial processing to a highly parallel bit-serial
processing with a large number of simple computing units.
In this paper, we improve the time space conversion bus bridge (TS-bridge), which is the
external interface of the super parallel SIMD processor,
with a pattern matching capability for table look-up operations.
This reduces the number of Huffman coding
clock cycles by 60% as compared with DSP because the necessary
can be carried out in table look-up clock cycles.
Keyword (in Japanese) (See Japanese page) 
(in English) super parallel SIMD processor / CAM / Huffman encoding / multimedia processing / pattern matching / / /  
Reference Info. IEICE Tech. Rep., vol. 106, no. 316, ICD2006-116, pp. 39-44, Oct. 2006.
Paper # ICD2006-116 
Date of Issue 2006-10-19 (SIP, ICD, IE) 
ISSN Print edition: ISSN 0913-5685
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Conference Information
Committee ICD SIP IE IPSJ-SLDM  
Conference Date 2006-10-26 - 2006-10-27 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2006-10-ICD-SIP-IE-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Super parallel SIMD processor with CAM based high-speed pattern matching capability 
Sub Title (in English)  
Keyword(1) super parallel SIMD processor  
Keyword(2) CAM  
Keyword(3) Huffman encoding  
Keyword(4) multimedia processing  
Keyword(5) pattern matching  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yutaka Kono  
1st Author's Affiliation Hiroshima University (Hiroshima Univ.)
2nd Author's Name Takeshi Kumaki  
2nd Author's Affiliation Hiroshima University (Hiroshima Univ.)
3rd Author's Name Masakatsu Ishizaki  
3rd Author's Affiliation Hiroshima University (Hiroshima Univ.)
4th Author's Name Masaharu Tagami  
4th Author's Affiliation Hiroshima University (Hiroshima Univ.)
5th Author's Name Tetsushi Koide  
5th Author's Affiliation Hiroshima University (Hiroshima Univ.)
6th Author's Name Hans Juergen Mattausch  
6th Author's Affiliation Hiroshima University (Hiroshima Univ.)
7th Author's Name Takayuki Gyohten  
7th Author's Affiliation Renesas Technology Corp. (Renesas)
8th Author's Name Hideyuki Noda  
8th Author's Affiliation Renesas Technology Corp. (Renesas)
9th Author's Name Yasuto Kuroda  
9th Author's Affiliation Renesas Technology Corp. (Renesas)
10th Author's Name Katsumi Dosaka  
10th Author's Affiliation Renesas Technology Corp. (Renesas)
11th Author's Name Kazutami Arimoto  
11th Author's Affiliation Renesas Technology Corp. (Renesas)
12th Author's Name Kazunori Saito  
12th Author's Affiliation Renesas Technology Corp. (Renesas)
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Speaker Author-1 
Date Time 2006-10-26 11:30:00 
Presentation Time 20 minutes 
Registration for ICD 
Paper # SIP2006-90, ICD2006-116, IE2006-68 
Volume (vol) vol.106 
Number (no) no.314(SIP), no.316(ICD), no.318(IE) 
Page pp.39-44 
#Pages
Date of Issue 2006-10-19 (SIP, ICD, IE) 


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