Conference Information |
Committee |
RECONF CPSY VLD DC IPSJ-SLDM IPSJ-ARC |
Conference Date |
2006-11-28 - 2006-11-30 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kitakyushu International Conference Center |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2006 ---A New Frontier in VLSI Design--- |
Paper Information |
Registration To |
VLD |
Conference Code |
2006-11-RECONF-CPSY-VLD-DC-IPSJ-SLDM-IPSJ-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Formal Verification Method for Arithmetic Circuits and Its Evaluation |
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1st Author's Name |
Yuki Watanabe |
1st Author's Affiliation |
Tohoku University (Tohoku Univ.) |
2nd Author's Name |
Naofumi Homma |
2nd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
3rd Author's Name |
Takafumi Aoki |
3rd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
4th Author's Name |
Tatsuo Higuchi |
4th Author's Affiliation |
Tohoku Institute of Technology (Totech) |
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Speaker |
Author-1 |
Date Time |
2006-11-28 10:15:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2006-54, DC2006-41 |
Volume (vol) |
vol.106 |
Number (no) |
no.387(VLD), no.390(DC) |
Page |
pp.17-22 |
#Pages |
6 |
Date of Issue |
2006-11-21 (VLD, DC) |