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Paper Abstract and Keywords
Presentation 2007-01-26 11:20
Development of pipelined bit-serial single-flux-quantum microprocessors
Masamitsu Tanaka (Nagoya Univ.), Yuki Yamanashi (Yokohama National Univ.), Naoki Irie (Nagoya Univ.), Heejoung Park (Yokohama National Univ.), Shingo Iwasaki (Nagoya Univ.), Kazuhiro Taketomi (Yokohama National Univ.), Akira Fujimaki (Nagoya Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.), Hirotaka Terai (NICT), Shinichi Yorozu (NEC)
Abstract (in Japanese) (See Japanese page) 
(in English) A pipelined single-flux-quantum microprocessor, called CORE1$\beta$ has been designed and its perfect operations have been demonstrated by on-chip high-speed testing. High performance-to-power consumption ratio is achieved in this microprocessor, because bit-serial processing is employed for 16-bit instructions and 8-bit data and the high-throughput nature of single-flux-quantum circuit is utilized. In order to realize a complex pipeline processing effectively, we separated the clock signals for bit operations and instruction execution, and developed several component circuits including a controller designed with use of one-hot encoding, a register file which can be written and read independently, buffers for ease of the timing design. The CORE1$\beta$ is a large-scale circuit made up of over 10,000 junctions. We eliminated the harmful effects due to the large bias current supplying by introducing fully superconductively-shielded cell library and an 8-mm square chip. The designed CORE1β has operated correctly up to 25 GHz and 17 GHz for bit operations of instructions and data, respectively, consuming 3.4 mW powers. The peak performance has been estimated to be 1400 million operations per second (MOPS).
Keyword (in Japanese) (See Japanese page) 
(in English) Superconductive Device / Single-Flux-Quantum Logic / SFQ / Microprocessor / / / /  
Reference Info. IEICE Tech. Rep., vol. 106, no. 503, SCE2006-33, pp. 19-24, Jan. 2007.
Paper # SCE2006-33 
Date of Issue 2007-01-19 (SCE) 
ISSN Print edition: ISSN 0913-5685
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Conference Information
Committee SCE  
Conference Date 2007-01-26 - 2007-01-26 
Place (in Japanese) (See Japanese page) 
Place (in English) SRL 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Digital electronics, etc 
Paper Information
Registration To SCE 
Conference Code 2007-01-SCE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Development of pipelined bit-serial single-flux-quantum microprocessors 
Sub Title (in English)  
Keyword(1) Superconductive Device  
Keyword(2) Single-Flux-Quantum Logic  
Keyword(3) SFQ  
Keyword(4) Microprocessor  
Keyword(5)  
Keyword(6)  
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1st Author's Name Masamitsu Tanaka  
1st Author's Affiliation Nagoya University (Nagoya Univ.)
2nd Author's Name Yuki Yamanashi  
2nd Author's Affiliation Yokohama National University (Yokohama National Univ.)
3rd Author's Name Naoki Irie  
3rd Author's Affiliation Nagoya University (Nagoya Univ.)
4th Author's Name Heejoung Park  
4th Author's Affiliation Yokohama National University (Yokohama National Univ.)
5th Author's Name Shingo Iwasaki  
5th Author's Affiliation Nagoya University (Nagoya Univ.)
6th Author's Name Kazuhiro Taketomi  
6th Author's Affiliation Yokohama National University (Yokohama National Univ.)
7th Author's Name Akira Fujimaki  
7th Author's Affiliation Nagoya University (Nagoya Univ.)
8th Author's Name Nobuyuki Yoshikawa  
8th Author's Affiliation Yokohama National University (Yokohama National Univ.)
9th Author's Name Hirotaka Terai  
9th Author's Affiliation National Institute of Information and Communications Technology (NICT)
10th Author's Name Shinichi Yorozu  
10th Author's Affiliation NEC Corporation (NEC)
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Speaker Author-1 
Date Time 2007-01-26 11:20:00 
Presentation Time 25 minutes 
Registration for SCE 
Paper # SCE2006-33 
Volume (vol) vol.106 
Number (no) no.503 
Page pp.19-24 
#Pages
Date of Issue 2007-01-19 (SCE) 


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