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| Paper Abstract and Keywords | ||
| Presentation | 2007-03-05 15:10 Evaluation and Discussion on Module Placement using Wire Length Aware Partially Ordered Sequence-Pair Yuuki Yano, Mineo Kaneko (JAIST)  CAS2006-88 SIP2006-189 CS2006-105 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In the module placement problem, the code representation of a placement called sequence-pair, and simulated annealing search of the solution space defined by the sequence-pair have been proposed. Due to the properties of sequence-pair and SA search, the computation time increases rapidly as the circuit size becomes large. As an approach to this problem, a solution space reduction using a model placement has been proposed. The model placement is obtained, for example, by computing a placement which minimizes total quadratic wire length. The solution space reduction is then achieved by transforming relative positions between modules in the model placement into constraints on sequence-pairs. In this paper, we conduct experiments of placement optimization based on the method mentioned above. This paper reports experimental results and discussions in the following issues: (1) The effect of removing overlaps between modules in the model placement, (2) the effect of the minimum distance between modules for which we extract relative position and transform it to a constraint on sequence-pair, and (3) comparison with normal sequence-pair. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Sequence-pair / simulated annealing / force-directed method / partial order / solution space reduction / overlap removal / / | |
| Reference Info. | IEICE Tech. Rep., vol. 106, no. 567, CAS2006-88, pp. 63-68, March 2007. | |
| Paper # | CAS2006-88 | |
| Date of Issue | 2007-02-26 (CAS, SIP, CS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2006-88 SIP2006-189 CS2006-105 |
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| Conference Information | |
| Committee | SIP CAS CS |
| Conference Date | 2007-03-05 - 2007-03-06 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Blancart Misasa (Tottori) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Signal Processing for Communications, Code Theory, etc. |
| Paper Information | |
| Registration To | CAS |
| Conference Code | 2007-03-SIP-CAS-CS |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation and Discussion on Module Placement using Wire Length Aware Partially Ordered Sequence-Pair |
| Sub Title (in English) | |
| Keyword(1) | Sequence-pair |
| Keyword(2) | simulated annealing |
| Keyword(3) | force-directed method |
| Keyword(4) | partial order |
| Keyword(5) | solution space reduction |
| Keyword(6) | overlap removal |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yuuki Yano |
| 1st Author's Affiliation | Japan Advanced Institute of Science and Technology (JAIST) |
| 2nd Author's Name | Mineo Kaneko |
| 2nd Author's Affiliation | Japan Advanced Institute of Science and Technology (JAIST) |
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| Speaker | Author-1 |
| Date Time | 2007-03-05 15:10:00 |
| Presentation Time | 25 minutes |
| Registration for | CAS |
| Paper # | CAS2006-88, SIP2006-189, CS2006-105 |
| Volume (vol) | vol.106 |
| Number (no) | no.567(CAS), no.569(SIP), no.571(CS) |
| Page | pp.63-68 |
| #Pages | 6 |
| Date of Issue | 2007-02-26 (CAS, SIP, CS) |
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