Paper Abstract and Keywords |
Presentation |
2007-03-09 09:20
Adaptive Reduction of Power Consumption of Viterbi Decoder using Reconfigurable Processor Yuken Kishimoto, Shinichiro Haruyama, Masao Nakagawa (Keio Univ.) SR2006-90 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In past time, the research that Viterbi decoder is achieved on VLSI was studied, but it was unique research that Viterbi decoder has changed constraint length or any other decode conditions. Using FPGA (Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device) which are traditional reprogrammable not need to prepare more decoding circuits, but there was a failure that it takes a long time to reconfigure the circuit. In this paper, we used Reconfigurable Processor DAPDNA-II and we had implemented Viterbi decoder among four constraint length from 3 to 6. In this paper, using Reconfigurable Processor, we assumed the shortening the reconfiguration time. In certain SNR, we had set the threshold of BER and performed the simulation of changing constraint length. In the result, when the throughput was fixed on 6.40Mbps, and the reconfiguration of circuit was performing frequently, it is compared with constraint length of the best performance, we had confirmed the reduction of power consumption about 40% - 80%. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Viterbi Decode / Software Defined Radio / Reconfigurable Processor / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 106, no. 558, SR2006-90, pp. 9-13, March 2007. |
Paper # |
SR2006-90 |
Date of Issue |
2007-03-02 (SR) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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SR2006-90 |
Conference Information |
Committee |
RCS MoNA WBS SR MW |
Conference Date |
2007-03-07 - 2007-03-09 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
YRP |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
SR |
Conference Code |
2007-03-RCS-MoMuC-WBS-SR-MW |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Adaptive Reduction of Power Consumption of Viterbi Decoder using Reconfigurable Processor |
Sub Title (in English) |
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Keyword(1) |
Viterbi Decode |
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Software Defined Radio |
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Reconfigurable Processor |
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1st Author's Name |
Yuken Kishimoto |
1st Author's Affiliation |
Keio University (Keio Univ.) |
2nd Author's Name |
Shinichiro Haruyama |
2nd Author's Affiliation |
Keio University (Keio Univ.) |
3rd Author's Name |
Masao Nakagawa |
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Keio University (Keio Univ.) |
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Speaker |
Author-1 |
Date Time |
2007-03-09 09:20:00 |
Presentation Time |
20 minutes |
Registration for |
SR |
Paper # |
SR2006-90 |
Volume (vol) |
vol.106 |
Number (no) |
no.558 |
Page |
pp.9-13 |
#Pages |
5 |
Date of Issue |
2007-03-02 (SR) |
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