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| Presentation | 2007-03-09 09:00 Effect of the Number of Wiring Layers on the Chip Area of Multipliers Hirotaka Kawashima, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.) Link to ES Tech. Rep. Archives:  ICD2006-232 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The number of metal layers usable for wiring is increasing because of the progress of manufacturing technologies of VLSI. The amount of interconnections which are wired above cells increases according to the increases of wiring layers. Since the area for interconnections is reduced, circuits can be designed with smaller area. Multiplication is one of the basic arithmetic operations and many ASICs have multipliers. Multipliers occupy large area in ASICs and the size and the manufacturing cost of ASICs is effected by the area of multipliers. We have designed multipliers using various implementation, and have investigated the effect of the number of wiring layers on the chip area of multipliers. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | multiplier / multilayer interconnection / wiring layer / circuit area / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 106, no. 549, VLD2006-141, pp. 7-11, March 2007. | |
| Paper # | VLD2006-141 | |
| Date of Issue | 2007-03-02 (VLD, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2006-232 |
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| Conference Information | |
| Committee | ICD VLD |
| Conference Date | 2007-03-07 - 2007-03-09 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Mielparque Okinawa |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System-on-silicon design techniques and related VLSs |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2007-03-ICD-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Effect of the Number of Wiring Layers on the Chip Area of Multipliers |
| Sub Title (in English) | |
| Keyword(1) | multiplier |
| Keyword(2) | multilayer interconnection |
| Keyword(3) | wiring layer |
| Keyword(4) | circuit area |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hirotaka Kawashima |
| 1st Author's Affiliation | Nagoya University (Nagoya Univ.) |
| 2nd Author's Name | Naofumi Takagi |
| 2nd Author's Affiliation | Nagoya University (Nagoya Univ.) |
| 3rd Author's Name | Kazuyoshi Takagi |
| 3rd Author's Affiliation | Nagoya University (Nagoya Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-03-09 09:00:00 |
| Presentation Time | 20 minutes |
| Registration for | VLD |
| Paper # | VLD2006-141, ICD2006-232 |
| Volume (vol) | vol.106 |
| Number (no) | no.549(VLD), no.552(ICD) |
| Page | pp.7-11 |
| #Pages | 5 |
| Date of Issue | 2007-03-02 (VLD, ICD) |
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