| Paper Abstract and Keywords |
| Presentation |
2007-05-10 13:55
Heuristic Instruction Scheduling Method for Processors with Partial Data Forwarding Structure
Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Partial forwarding is a design method to put forwarding paths on a part of processor pipeline.
To schedule instructions considering partial forwarding structure, the designer can reduce hardware cost of the processor without performance loss by design space exploration of the forwarding structure on a processor.
Though a scheduling method with integer linear programming method for partial forwarding processor has already been proposed, compilation may not complete against large programs.
In this paper, we propose a heuristic instruction scheduling method for processors with partial forwarding structure.
Experimental results show that the proposed method can generate almost optimal scheduling results in short time and optimal solution candidates with the proposed method are the same as those with the integer linear programming method in design space exploration. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Partial forwarding / Instruction scheduling / Compiler / Design space exploration / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 107, pp. 7-12, May 2007. |
| Paper # |
|
| Date of Issue |
2007-05-03 (VLD) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
| Download PDF |
|
| Conference Information |
| Committee |
VLD IPSJ-SLDM |
| Conference Date |
2007-05-10 - 2007-05-11 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Kyodai Kaikan |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
System Design, etc. |
| Paper Information |
| Registration To |
IPSJ-SLDM |
| Conference Code |
2007-05-VLD-IPSJ-SLDM |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Heuristic Instruction Scheduling Method for Processors with Partial Data Forwarding Structure |
| Sub Title (in English) |
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| Keyword(1) |
Partial forwarding |
| Keyword(2) |
Instruction scheduling |
| Keyword(3) |
Compiler |
| Keyword(4) |
Design space exploration |
| Keyword(5) |
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| Keyword(6) |
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| 1st Author's Name |
Takuji Hieda |
| 1st Author's Affiliation |
Osaka University (Osaka Univ.) |
| 2nd Author's Name |
Hiroaki Tanaka |
| 2nd Author's Affiliation |
Osaka University (Osaka Univ.) |
| 3rd Author's Name |
Keishi Sakanushi |
| 3rd Author's Affiliation |
Osaka University (Osaka Univ.) |
| 4th Author's Name |
Yoshinori Takeuchi |
| 4th Author's Affiliation |
Osaka University (Osaka Univ.) |
| 5th Author's Name |
Masaharu Imai |
| 5th Author's Affiliation |
Osaka University (Osaka Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2007-05-10 13:55:00 |
| Presentation Time |
25 minutes |
| Registration for |
IPSJ-SLDM |
| Paper # |
VLD2007-2 |
| Volume (vol) |
vol.107 |
| Number (no) |
no.31 |
| Page |
pp.7-12 |
| #Pages |
6 |
| Date of Issue |
2007-05-03 (VLD) |