Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2007-05-11 10:20
A Clock Deskew Method using PDE with Discrete Delay
Yuko Hashizume, Naoki Otani, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) VLD2007-9
Abstract (in Japanese) (See Japanese page) 
(in English) In deep-submicron technology, process variations can severely affect the performance and the yield of VLSI chips. As a countermeasure to the variations, deskew, which inserts Programmable Delay Elements (PDEs) into the clock tree and adjusts the clock arrival times of FFs, has been proposed. One of the previous deskew methods measures the arrival clock times of small amount of FFs and presumes that of the others under the assumption that process variation follows Gaussian distribution. This method assumed that PDEs have continuous delay value. We extend this method to handle PDEs which have discrete delay value. We utilize that the constraints hold totally unimodular and decide the delay values of PDEs by the linear programming. Our experiments show that the yield is improved from 19.4% to 85.4% after applying deskew method for a sample when the arrival times for 0.15% of total FFs are measured and the delays of 16 PDEs with delay steps of 30ps are tuned.
Keyword (in Japanese) (See Japanese page) 
(in English) Deskew / Programmable Delay Element(PDE) / Linear Programming / Gaussian Distribution / Totally Unimodular / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 32, VLD2007-9, pp. 13-18, May 2007.
Paper # VLD2007-9 
Date of Issue 2007-05-04 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-9

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2007-05-10 - 2007-05-11 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyodai Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2007-05-VLD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Clock Deskew Method using PDE with Discrete Delay 
Sub Title (in English)  
Keyword(1) Deskew  
Keyword(2) Programmable Delay Element(PDE)  
Keyword(3) Linear Programming  
Keyword(4) Gaussian Distribution  
Keyword(5) Totally Unimodular  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yuko Hashizume  
1st Author's Affiliation The University of Kitakyushu (Univ. of Kitakyushu)
2nd Author's Name Naoki Otani  
2nd Author's Affiliation The University of Kitakyushu (Univ. of Kitakyushu)
3rd Author's Name Yasuhiro Takashima  
3rd Author's Affiliation The University of Kitakyushu (Univ. of Kitakyushu)
4th Author's Name Yuichi Nakamura  
4th Author's Affiliation NEC (NEC)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2007-05-11 10:20:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2007-9 
Volume (vol) vol.107 
Number (no) no.32 
Page pp.13-18 
#Pages 6 
Date of Issue 2007-05-04 (VLD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan