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Paper Abstract and Keywords
Presentation 2007-05-11 13:45
A fast maximum delay estimation method for specified yield by statistical static timing analysis.
Hiroki Furuya, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) VLD2007-14
Abstract (in Japanese) (See Japanese page) 
(in English) As VLSI technology advances, the variation of an element delay
caused by manufacturing and circuit operation increases.
Under such circumstance, it becomes difficult to obtain
a high performance circuit by using the conventional worst case
delay analysis because the excessive design margin is required.
Therefore, Statistical Static Timing Analysis (SSTA)
becomes a popular method. However, the circuit delay
estimated by using conventional SSTA in which the average and variance
of distribution are estimated is often underestimated,
and the specified circuit yield often cannot be achieved.
In this paper, we focus on MAX-operation used in delay estimation,
and show the condition that the conventional MAX-operation
underestimates the maximum delay.
Then, we propose a maximum delay estimation method for specified yield
in which MAX-operation is modified.
In experiments, by Monte-Carlo simulation,
it is shown that the circuit yield
by the maximum delay estimated by the proposed method
approaches the specification compared to that by the conventional method.
Keyword (in Japanese) (See Japanese page) 
(in English) Statisticl Static Timing Analysis / Maximum delay / MAX-operation / Yield / Gaussian distribution / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 32, VLD2007-14, pp. 43-47, May 2007.
Paper # VLD2007-14 
Date of Issue 2007-05-04 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-14

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2007-05-10 - 2007-05-11 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyodai Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2007-05-VLD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A fast maximum delay estimation method for specified yield by statistical static timing analysis. 
Sub Title (in English)  
Keyword(1) Statisticl Static Timing Analysis  
Keyword(2) Maximum delay  
Keyword(3) MAX-operation  
Keyword(4) Yield  
Keyword(5) Gaussian distribution  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroki Furuya  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Yukihide Kohira  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
3rd Author's Name Atsushi Takahashi  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Speaker Author-1 
Date Time 2007-05-11 13:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2007-14 
Volume (vol) vol.107 
Number (no) no.32 
Page pp.43-47 
#Pages 5 
Date of Issue 2007-05-04 (VLD) 

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