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Paper Abstract and Keywords
Presentation 2007-05-17 17:20
A Discussion on a Router for embedded Programmable Logic matriX (ePLX)
Naoki Okuno, Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.), Takenobu Iwao, Hirofumi Nakano, Yoshihiro Okuno, Kazutami Arimoto (Renesas) RECONF2007-9
Abstract (in Japanese) (See Japanese page) 
(in English) We propose a fine-grained programmable logic architecture designed to be embedded in system-on-chips (SoCs) to enhance the performance maintaining the programmability. The ePLX consists of Look-Up-Table(LUT) arrays and hierarchical wiring resources connecting them. In order to implement a target function on the ePLX, we need a set of computer-aided design tools. This paper presents a fundamental discussion on an automated router for interconnection blocks. Since the interconnection block has hierarchical and repeated structure and there may be variations of the structure, we define an efficient format to describe the architecture of the interconnection block and provide it to our router. We construct a basic framework of routing algorithms where one net is selected and (re)routed one by one.
Keyword (in Japanese) (See Japanese page) 
(in English) System-on-Chip / Programmable Logic / Computer Aided Design / Router / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 41, RECONF2007-9, pp. 49-54, May 2007.
Paper # RECONF2007-9 
Date of Issue 2007-05-10 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2007-9

Conference Information
Committee RECONF  
Conference Date 2007-05-17 - 2007-05-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Kanazawa Bunka Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2007-05-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Discussion on a Router for embedded Programmable Logic matriX (ePLX) 
Sub Title (in English)  
Keyword(1) System-on-Chip  
Keyword(2) Programmable Logic  
Keyword(3) Computer Aided Design  
Keyword(4) Router  
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1st Author's Name Naoki Okuno  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Tomonori Izumi  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
3rd Author's Name Takeshi Fujino  
3rd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
4th Author's Name Takenobu Iwao  
4th Author's Affiliation Renesas Technology (Renesas)
5th Author's Name Hirofumi Nakano  
5th Author's Affiliation Renesas Technology (Renesas)
6th Author's Name Yoshihiro Okuno  
6th Author's Affiliation Renesas Technology (Renesas)
7th Author's Name Kazutami Arimoto  
7th Author's Affiliation Renesas Technology (Renesas)
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Speaker Author-1 
Date Time 2007-05-17 17:20:00 
Presentation Time 30 minutes 
Registration for RECONF 
Paper # RECONF2007-9 
Volume (vol) vol.107 
Number (no) no.41 
Page pp.49-54 
#Pages 6 
Date of Issue 2007-05-10 (RECONF) 

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