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Paper Abstract and Keywords
Presentation 2007-05-18 11:10
*
Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ.) RECONF2007-14
Abstract (in Japanese) (See Japanese page) 
(in English) A new architecture of parallel processor is proposed, whose processing element can support various types of operations in a reconfigurable manner. The processor is suitable for the intelligent image processing, such as, high-performance geometry and matching operations in pattern recognition using 3D models. The processing element is constructed from 26 4bit-adder subunits and other elementary subunits. The connections of each subunit and between processing elements are mainly realized by input-selectors and crossbar network. By changing crossbar or selector switches, the configuration and the function of the element can be changed from integer adders to integer multipliers or floating-point unit. The peak performance of single processing element is 1 BOPS (byte-integer operations) or 125MFLOPS at 250MHz clock frequency.
Keyword (in Japanese) (See Japanese page) 
(in English) Reconfigurable Processor / Arithmetic Unit / FPU / Crossbar / Image Processing / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 41, RECONF2007-14, pp. 79-84, May 2007.
Paper # RECONF2007-14 
Date of Issue 2007-05-10 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2007-14

Conference Information
Committee RECONF  
Conference Date 2007-05-17 - 2007-05-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Kanazawa Bunka Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2007-05-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) * 
Sub Title (in English)  
Keyword(1) Reconfigurable Processor  
Keyword(2) Arithmetic Unit  
Keyword(3) FPU  
Keyword(4) Crossbar  
Keyword(5) Image Processing  
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1st Author's Name Hiroshi Kadota  
1st Author's Affiliation Kyushu University (Kyushu Univ.)
2nd Author's Name Akiyoshi Wakatani  
2nd Author's Affiliation Konan University (Konan Univ.)
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Speaker Author-1 
Date Time 2007-05-18 11:10:00 
Presentation Time 30 minutes 
Registration for RECONF 
Paper # RECONF2007-14 
Volume (vol) vol.107 
Number (no) no.41 
Page pp.79-84 
#Pages 6 
Date of Issue 2007-05-10 (RECONF) 

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