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| Paper Abstract and Keywords | ||
| Presentation | 2007-05-31 11:30 The Potential of Temperature-Aware Configurable Cache on Energy Reduction Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) Link to ES Tech. Rep. Archives:  ICD2007-19 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of digital systems continues to grow. Moreover, temperature is another factor that exponentially increases the leakage current. In this paper, we show the effects of temperature and technology nodes on the optimal (minimum-energy-consuming) cache configuration for low energy embedded systems. We show that a temperature-aware configurable cache is an effective way to save energy in finer technologies when the embedded system may be used in different temperatures. Our results show that using a temperature-aware configurable cache, up to 66% energy can be saved with only 1% performance penalty for instruction cache and 74% energy saving with 4.7% performance loss for data cache. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Low Power / Cache / Temperature / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, pp. 13-18, May 2007. | |
| Paper # | ||
| Date of Issue | 2007-05-24 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2007-19 |
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| Conference Information | |
| Committee | ICD IPSJ-ARC |
| Conference Date | 2007-05-31 - 2007-06-01 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Creative Collaboration between Circuit and Architecture: Processor, Memory and SOC |
| Paper Information | |
| Registration To | IPSJ-ARC |
| Conference Code | 2007-05-ICD-IPSJ-ARC |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The Potential of Temperature-Aware Configurable Cache on Energy Reduction |
| Sub Title (in English) | |
| Keyword(1) | Low Power |
| Keyword(2) | Cache |
| Keyword(3) | Temperature |
| Keyword(4) | |
| Keyword(5) | |
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| 1st Author's Name | Hamid Noori |
| 1st Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 2nd Author's Name | Maziar Goudarzi |
| 2nd Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 3rd Author's Name | Koji Inoue |
| 3rd Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 4th Author's Name | Kazuaki Murakami |
| 4th Author's Affiliation | Kyushu University (Kyushu Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-05-31 11:30:00 |
| Presentation Time | 30 minutes |
| Registration for | IPSJ-ARC |
| Paper # | ICD2007-19 |
| Volume (vol) | vol.107 |
| Number (no) | no.76 |
| Page | pp.13-18 |
| #Pages | 6 |
| Date of Issue | 2007-05-24 (ICD) |
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