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Paper Abstract and Keywords
Presentation 2007-07-20 09:55
A Simple Countermeasure to DPA aginst FPGA Implementation of Cryptographic Device
Janghoon Song, Koki Abe (UEC) ISEC2007-45
Abstract (in Japanese) (See Japanese page) 
(in English) Random Switching Logic is a countermeasure to DPA that removes the relation between data and power consumption by making the transition probability of each gate uniform using random numbers.
In this paper, we applied a countermeasure to DPA against cryptographic devices implemented on FPGA.
The countermeasure removes the relation between data and power consumption by making the transition probability of each operation instead of each gate.
Results of experiments reveal that the countermeasure improves the DPA resistance.．
Considering that an operation module is placed on multiple LUTs, the results imply that the relation between information leak and power consumption of FPGA interconnects of switching matrix is insignificant.
Implementation of the countermeasure is simple because the circuits are modularized at operation level instead of gate level.
Keyword (in Japanese) (See Japanese page) 
(in English) Side-channel Attack / Differential Power Analysis / FPGA / Countermeasure at Operation Level / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 141, ISEC2007-45, pp. 1-8, July 2007.
Paper # ISEC2007-45 
Date of Issue 2007-07-13 (ISEC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ISEC2007-45

Conference Information
Committee ISEC SITE IPSJ-CSEC  
Conference Date 2007-07-19 - 2007-07-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Future University-Hakodate 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ISEC 
Conference Code 2007-07-ISEC-SITE-IPSJ-CSEC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Simple Countermeasure to DPA aginst FPGA Implementation of Cryptographic Device 
Sub Title (in English)  
Keyword(1) Side-channel Attack  
Keyword(2) Differential Power Analysis  
Keyword(3) FPGA  
Keyword(4) Countermeasure at Operation Level  
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Keyword(6)  
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Keyword(8)  
1st Author's Name Janghoon Song  
1st Author's Affiliation The University of Electro-Communications (UEC)
2nd Author's Name Koki Abe  
2nd Author's Affiliation The University of Electro-Communications (UEC)
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Speaker Author-1 
Date Time 2007-07-20 09:55:00 
Presentation Time 25 minutes 
Registration for ISEC 
Paper # ISEC2007-45 
Volume (vol) vol.107 
Number (no) no.141 
Page pp.1-8 
#Pages 8 
Date of Issue 2007-07-13 (ISEC) 

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