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Paper Abstract and Keywords
Presentation 2007-07-20 11:40
A Novel Design Methodology of the On-Chip Power Distribution Network greatly improving Performance and EMC of the SoC
Hirokazu Tohya, Noritaka Toya (ICAST) EE2007-20
Abstract (in Japanese) (See Japanese page) 
(in English) The novel concept about the solitary electromagnetic wave (SEMW) is presented. The SEMW is generated by the on-chip inverter, and its waveform is similar to a half-wave of the sinusoidal. It is assumed from the generation mechanism that the SEMW is a kind of soliton. A design example of the on-chip power distribution network (PDN) by applying the SEMW concept is also presented. The novel low-impedance lossy line (LILL) technology is used for the on-chip PDN instead of the conventional on-chip capacitors. It can improve the performance of the SoC and it can also solve the EMC problem about the PDN remarkably.
Keyword (in Japanese) (See Japanese page) 
(in English) on-chip PDN / on-chip inverter / SoC / MPU / EMC / soliton / interconnect / decoupling  
Reference Info. IEICE Tech. Rep., vol. 107, no. 149, EE2007-20, pp. 73-78, July 2007.
Paper # EE2007-20 
Date of Issue 2007-07-12 (EE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF EE2007-20

Conference Information
Committee EE  
Conference Date 2007-07-19 - 2007-07-20 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To EE 
Conference Code 2007-07-EE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Novel Design Methodology of the On-Chip Power Distribution Network greatly improving Performance and EMC of the SoC 
Sub Title (in English)  
Keyword(1) on-chip PDN  
Keyword(2) on-chip inverter  
Keyword(3) SoC  
Keyword(4) MPU  
Keyword(5) EMC  
Keyword(6) soliton  
Keyword(7) interconnect  
Keyword(8) decoupling  
1st Author's Name Hirokazu Tohya  
1st Author's Affiliation ICAST, Inc. (ICAST)
2nd Author's Name Noritaka Toya  
2nd Author's Affiliation ICAST, Inc. (ICAST)
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Speaker Author-1 
Date Time 2007-07-20 11:40:00 
Presentation Time 30 minutes 
Registration for EE 
Paper # EE2007-20 
Volume (vol) vol.107 
Number (no) no.149 
Page pp.73-78 
#Pages 6 
Date of Issue 2007-07-12 (EE) 

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