| Paper Abstract and Keywords |
| Presentation |
2007-07-27 08:30
A Study of Clock and Data Recovery Circuits with Wide Band VCO Tomoyuki Tanaka (Osaka Univ./Synthesis), Tsukasa Ida, Guechol Kim, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) ICD2007-54 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
We proposed wide band Clock and Data Recovery circuits (CDR) with VCO-control-voltage recovery block which avoid the loop to fall out of lock and pseudo-lock.
SPICE simulations of the designed CDR in a mixed-signal 0.25um CMOS process with a single 3.3V power supply successfully demonstrated the recovery of
clock for the data-rate up to 1.6 times(fmax/fmin). |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
CDR / VCO control voltage / VCO control voltage recovery circuits / Schmitt trigger / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 107, no. 163, ICD2007-54, pp. 101-105, July 2007. |
| Paper # |
ICD2007-54 |
| Date of Issue |
2007-07-19 (ICD) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Download PDF |
ICD2007-54 |
| Conference Information |
| Committee |
ICD ITE-IST |
| Conference Date |
2007-07-26 - 2007-07-27 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
|
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
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| Paper Information |
| Registration To |
ICD |
| Conference Code |
2007-07-ICD-ITE-IST |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
A Study of Clock and Data Recovery Circuits with Wide Band VCO |
| Sub Title (in English) |
|
| Keyword(1) |
CDR |
| Keyword(2) |
VCO control voltage |
| Keyword(3) |
VCO control voltage recovery circuits |
| Keyword(4) |
Schmitt trigger |
| Keyword(5) |
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| Keyword(6) |
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| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Tomoyuki Tanaka |
| 1st Author's Affiliation |
Osaka University/Synthesis (Osaka Univ./Synthesis) |
| 2nd Author's Name |
Tsukasa Ida |
| 2nd Author's Affiliation |
Osaka University (Osaka Univ.) |
| 3rd Author's Name |
Guechol Kim |
| 3rd Author's Affiliation |
Osaka University (Osaka Univ.) |
| 4th Author's Name |
Toshimasa Matsuoka |
| 4th Author's Affiliation |
Osaka University (Osaka Univ.) |
| 5th Author's Name |
Kenji Taniguchi |
| 5th Author's Affiliation |
Osaka University (Osaka Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2007-07-27 08:30:00 |
| Presentation Time |
25 minutes |
| Registration for |
ICD |
| Paper # |
ICD2007-54 |
| Volume (vol) |
vol.107 |
| Number (no) |
no.163 |
| Page |
pp.101-105 |
| #Pages |
5 |
| Date of Issue |
2007-07-19 (ICD) |