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Paper Abstract and Keywords
Presentation 2007-07-27 16:55
Studies on the Phase Noise and Spurious Level Behavior of an All Digital Phase Locked Loop
Michael Zamrowski (Johannes Gutenberg Univ.), Tsuyoshi Terao, Kiyomichi Araki (Tokyo Inst. of Tech.) SR2007-45
Abstract (in Japanese) (See Japanese page) 
(in English) An All Digital Phase Locked Loop (ADPLL) was proposed being suitable for a CMOS processed system on one chip digital RF transceiver. We analyzed the phase noise and the spurious behavior of the ADPLL depending on the components like the Digital Controlled Oscillator (DCO), the Time to Digital Converter (TDC), and the Loop filter. We also investigated the relation between the latch-up time and the phase noise and the spurious level. We attempted to verify the analysis results with the former simulation results.
Keyword (in Japanese) (See Japanese page) 
(in English) ADPLL / PLL / Digital RF / Loop Filter / DCO / TDC / Sigma-Delta Modulation /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 162, SR2007-45, pp. 157-162, July 2007.
Paper # SR2007-45 
Date of Issue 2007-07-19 (SR) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SR2007-45

Conference Information
Committee SR  
Conference Date 2007-07-26 - 2007-07-27 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SR 
Conference Code 2007-07-SR 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Studies on the Phase Noise and Spurious Level Behavior of an All Digital Phase Locked Loop 
Sub Title (in English)  
Keyword(1) ADPLL  
Keyword(2) PLL  
Keyword(3) Digital RF  
Keyword(4) Loop Filter  
Keyword(5) DCO  
Keyword(6) TDC  
Keyword(7) Sigma-Delta Modulation  
Keyword(8)  
1st Author's Name Michael Zamrowski  
1st Author's Affiliation Johannes Gutenberg Univ. (Johannes Gutenberg Univ.)
2nd Author's Name Tsuyoshi Terao  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
3rd Author's Name Kiyomichi Araki  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
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Speaker Author-1 
Date Time 2007-07-27 16:55:00 
Presentation Time 25 minutes 
Registration for SR 
Paper # SR2007-45 
Volume (vol) vol.107 
Number (no) no.162 
Page pp.157-162 
#Pages 6 
Date of Issue 2007-07-19 (SR) 

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